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1. 发明申请

US20100128831A1 CIRCUIT FOR DETECTING CLOCK AND APPARATUS FOR PROVIDING CLOCK 有权
标题翻译：用于检测时钟的电路和提供时钟的设备
公开(公告)号：US20100128831A1
公开(公告)日：2010-05-27
申请号：US12468248
申请日：2009-05-19
申请人： TSUNG-HSI LEE , Hung-Jen Tsai
发明人： TSUNG-HSI LEE , Hung-Jen Tsai
IPC分类号： H04L7/02
CPC分类号： G06F11/1604
摘要： A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last first transmission element for receiving output data, and the data received by each first transmission element is transmitted to an input terminal of a next first transmission element. In addition, the input of a first transmission element is coupled to a clock source for receiving a predetermined clock signal of which a frequency is less than a frequency of a local clock signal. Furthermore, the first and second input terminals of a kth exclusive OR gate are coupled to output terminals of a kth and a (k+1)th first transmission elements, wherein k is an integer greater than 0 smaller than a total number of the first transmission elements.
摘要翻译：用于检测时钟的电路具有多个第一传输元件，多个第一异或门和第一与门。每个第一传输元件被耦合到用于接收输出数据的最后的第一传输元件，并且由每个第一传输元件接收的数据被发送到下一个第一传输元件的输入端。此外，第一传输元件的输入耦合到时钟源，用于接收频率小于本地时钟信号频率的预定时钟信号。此外，第k个异或门的第一和第二输入端耦合到第k和第（k + 1）个第一传输元件的输出端，其中k是大于0的整数，小于第一传输元件

2. 发明授权

US06687725B1 Arithmetic circuit for finite field GF (2m) 有权
标题翻译：有限域GF（2m）的算术电路
公开(公告)号：US06687725B1
公开(公告)日：2004-02-03
申请号：US09605100
申请日：2000-06-23
申请人： Tung-Chou Chen , Shyue-Win Wei , Hung-Jen Tsai
发明人： Tung-Chou Chen , Shyue-Win Wei , Hung-Jen Tsai
IPC分类号： G06F700
CPC分类号： G06F7/724 , G06F7/726
摘要： An arithmetic unit which performs all basic arithmetic operations in a finite field GF(2m) and includes an arithmetic processor, an arithmetic logic unit and a control unit is disclosed. The arithmetic unit of the present invention is structured with a low circuit complexity, so that an error-correcting decoder applying this calculating processor can be greatly simplified.
摘要翻译：公开了一种在有限域GF（2）中执行所有基本算术运算并包括运算处理器，算术逻辑单元和控制单元的算术单元。本发明的算术单元被构造成具有低电路复杂度，使得可以极大地简化应用该计算处理器的纠错解码器。

3. 发明授权

US08351557B2 Circuit for detecting clock and apparatus for providing clock 有权
标题翻译：用于检测提供时钟的时钟和设备的电路
公开(公告)号：US08351557B2
公开(公告)日：2013-01-08
申请号：US12468248
申请日：2009-05-19
申请人： Tsung-Hsi Lee , Hung-Jen Tsai
发明人： Tsung-Hsi Lee , Hung-Jen Tsai
IPC分类号： H04L7/00
CPC分类号： G06F11/1604
摘要： A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last first transmission element for receiving output data, and the data received by each first transmission element is transmitted to an input terminal of a next first transmission element. In addition, the input of a first transmission element is coupled to a clock source for receiving a predetermined clock signal of which a frequency is less than a frequency of a local clock signal. Furthermore, the first and second input terminals of a kth exclusive OR gate are coupled to output terminals of a kth and a (k+1)th first transmission elements, wherein k is an integer greater than 0 smaller than a total number of the first transmission elements.
摘要翻译：用于检测时钟的电路具有多个第一传输元件，多个第一异或门和第一与门。每个第一传输元件被耦合到用于接收输出数据的最后的第一传输元件，并且由每个第一传输元件接收的数据被发送到下一个第一传输元件的输入端。此外，第一传输元件的输入耦合到时钟源，用于接收频率小于本地时钟信号频率的预定时钟信号。此外，第k个异或门的第一和第二输入端耦合到第k和第（k + 1）个第一传输元件的输出端，其中k是大于0的整数，小于第一传输元件

4. 发明授权

US5854134A Passivation layer for a metal film to prevent metal corrosion 失效
标题翻译：钝化层为金属膜防止金属腐蚀
公开(公告)号：US5854134A
公开(公告)日：1998-12-29
申请号：US851399
申请日：1997-05-05
申请人： Chao-Yi Lan , Shean-Ren Horng , Yun-Hung Shen , Hung-Jen Tsai
发明人： Chao-Yi Lan , Shean-Ren Horng , Yun-Hung Shen , Hung-Jen Tsai
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/302
CPC分类号： H01L21/02071
摘要： The invention provides a method of fabricating corrosion free metal lines. The method involves forming a thin polymeric passivation layer 30 over the metal layer 20 immediately after the metal deposition and before any photolithographic or etching processes. The polymeric passivation layer 30 is formed using a F-containing gas plasma treatment. The passivation layer prevents corrosion of the metal layer before a metal etch. The passivation layer is preferably composed of a polymeric of C, O, and F and has a thickness in a range of between about 40 and 80 .ANG.. The passivation layer is formed using a F-containing plasma treatment at a power of between 225 and 275 W, a pressure between about 80 and 120 mtorr, a CHF.sub.3 flow between about 40 and 60 sccm and for a duration between about 10 to 30 seconds. Following this, the metal layer is patterned using photo and etch steps.
摘要翻译：本发明提供一种制造无腐蚀金属线的方法。该方法包括在金属沉积之后和在任何光刻或蚀刻工艺之前立即在金属层20上形成薄的聚合物钝化层30。使用含F气体等离子体处理形成聚合物钝化层30。钝化层在金属蚀刻之前防止金属层的腐蚀。钝化层优选由C，O和F的聚合物组成，并且具有在约40至80埃范围内的厚度。钝化层使用含氟等离子体处理形成，功率为225-275W，压力为约80至120毫托，CHF 3流量为约40至60sccm，持续时间为约10至30秒。之后，使用光刻和蚀刻步骤对金属层进行构图。

5. 发明授权

US06472235B1 Apparatus and method for preparing backside-ground wafers for testing 有权
标题翻译：制备用于测试的背面晶片的装置和方法
公开(公告)号：US06472235B1
公开(公告)日：2002-10-29
申请号：US09886881
申请日：2001-06-21
申请人： Kuang-Peng Lin , Hung-Jen Tsai , Hsien-Tsong Liu
发明人： Kuang-Peng Lin , Hung-Jen Tsai , Hsien-Tsong Liu
IPC分类号： H01L2166
CPC分类号： B81C99/0035 , B81C1/00611 , B81C2201/0126 , Y10S438/959
摘要： A method and an apparatus for preparing a backside-ground wafer for testing are described. The method includes the steps of first providing a calibration wafer that has a pattern formed on a top surface of an insulating material such as oxide or nitride. Three droplets of water are applied with each droplet sufficiently apart from the other droplets on the top surface of the calibration wafer. A backside-ground wafer that has a ground backside and a front side to be tested is then mated to the calibration wafer by mating the ground backside to the top surface of the calibration wafer with water droplets therein-between forming a bond by capillary reaction in-between the oxide pattern on the calibration wafer. The apparatus for mounting a backside-ground wafer to a calibration wafer consists of a slanted block having a top surface with a slant angle between about 10° and about 30°.
摘要翻译：描述了用于制备用于测试的背面晶片的方法和装置。该方法包括以下步骤：首先提供具有形成在诸如氧化物或氮化物的绝缘材料的顶表面上的图案的校准晶片。每个液滴与校准晶片的顶表面上的其它液滴充分分开地施加三滴水。将具有接地背面和待测试的前侧的背面晶片然后通过将地面背面与校准晶片的顶表面配合而与校准晶片配合，并通过毛细管反应形成键 - 在校准晶片上的氧化物图案之间。用于将背面晶片安装到校准晶片的装置包括具有在大约10°至大约30°之间的倾斜角的顶表面的倾斜块。

6. 发明授权

US07202899B2 Method to prevent white pixels in a CMOS image sensor 有权
标题翻译：防止CMOS图像传感器中白色像素的方法
公开(公告)号：US07202899B2
公开(公告)日：2007-04-10
申请号：US10152469
申请日：2002-05-21
申请人： Kuen-Hsien Lin , Shang-Hsuan Liu , Chih-Hsing Chen , Hung Jen Tsai , Hsien-Tsong Liu
发明人： Kuen-Hsien Lin , Shang-Hsuan Liu , Chih-Hsing Chen , Hung Jen Tsai , Hsien-Tsong Liu
IPC分类号： H04N3/14
CPC分类号： H01L27/14687 , H01L27/14603 , H01L27/14609 , H01L27/14643
摘要： A method and system for preventing white pixel difficulties resulting from undesired current induced in an image sensor having a photodiode and a depletion region therein. The photodiode is isolated in a pixel layout for an image sensor. A depletion region is configured, such that the depletion region is maintained in a defect-free region associated with the pixel layout for the image sensor, thereby reducing white pixel difficulties caused by induced and undesired current. The image sensor is preferably a CMOS image sensor. A depletion region of the photodiode is constantly maintained in a defect-free region during operation of the CMOS image sensor.
摘要翻译：一种用于防止由于在其中具有光电二极管和耗尽区域的图像传感器中感应出不期望的电流导致的白色像素困难的方法和系统。在图像传感器的像素布局中隔离光电二极管。耗尽区域被配置为使得耗尽区域保持在与图像传感器的像素布局相关联的无缺陷区域中，从而减少由感应和不期望的电流引起的白色像素困难。图像传感器优选为CMOS图像传感器。在CMOS图像传感器的操作期间，光电二极管的耗尽区域始终保持在无缺陷区域中。

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