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1. 发明授权

US08351557B2 Circuit for detecting clock and apparatus for providing clock 有权
标题翻译：用于检测提供时钟的时钟和设备的电路
公开(公告)号：US08351557B2
公开(公告)日：2013-01-08
申请号：US12468248
申请日：2009-05-19
申请人： Tsung-Hsi Lee , Hung-Jen Tsai
发明人： Tsung-Hsi Lee , Hung-Jen Tsai
IPC分类号： H04L7/00
CPC分类号： G06F11/1604
摘要： A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last first transmission element for receiving output data, and the data received by each first transmission element is transmitted to an input terminal of a next first transmission element. In addition, the input of a first transmission element is coupled to a clock source for receiving a predetermined clock signal of which a frequency is less than a frequency of a local clock signal. Furthermore, the first and second input terminals of a kth exclusive OR gate are coupled to output terminals of a kth and a (k+1)th first transmission elements, wherein k is an integer greater than 0 smaller than a total number of the first transmission elements.
摘要翻译：用于检测时钟的电路具有多个第一传输元件，多个第一异或门和第一与门。每个第一传输元件被耦合到用于接收输出数据的最后的第一传输元件，并且由每个第一传输元件接收的数据被发送到下一个第一传输元件的输入端。此外，第一传输元件的输入耦合到时钟源，用于接收频率小于本地时钟信号频率的预定时钟信号。此外，第k个异或门的第一和第二输入端耦合到第k和第（k + 1）个第一传输元件的输出端，其中k是大于0的整数，小于第一传输元件

2. 发明授权

US08130563B2 Computer apparatus and memory error signal detecting system 有权
标题翻译：计算机设备和存储器错误信号检测系统
公开(公告)号：US08130563B2
公开(公告)日：2012-03-06
申请号：US12759345
申请日：2010-04-13
申请人： Tsung-Hsi Lee
发明人： Tsung-Hsi Lee
IPC分类号： G11C7/10
CPC分类号： G06F11/0751 , G06F11/073
摘要： A memory error signal detecting system including a signal extracting circuit, a flip-flop, a latch circuit, and a light sign is provided. The signal extracting circuit receives a memory error signal to output a pulse signal when the memory error signal switches from a first level to a second level. When the preset end of the flip-flop receives the pulse signal, and the maintaining time of the pulse signal is maintained for a predetermine time, the flip-flop output end is set to a high voltage level. The latch circuit determines whether to output the state of the flip-flop output according to the reset signal. The light sign operates according to the state of an output end of the latch circuit. Furthermore, a computer apparatus including the memory error signal detecting system is also provided.
摘要翻译：提供了包括信号提取电路，触发器，锁存电路和光标志的存储器误差信号检测系统。当存储器误差信号从第一电平切换到第二电平时，信号提取电路接收存储器误差信号以输出脉冲信号。当触发器的预设端接收到脉冲信号，并且脉冲信号的保持时间保持预定时间时，触发器输出端被设置为高电压电平。锁存电路根据复位信号确定是否输出触发器输出的状态。光符号根据锁存电路的输出端的状态来工作。此外，还提供了包括存储器错误信号检测系统的计算机装置。

3. 发明申请

US20120056852A1 ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF 审中-公开
标题翻译：电子装置及其控制方法
公开(公告)号：US20120056852A1
公开(公告)日：2012-03-08
申请号：US13118601
申请日：2011-05-31
申请人： Tsung-Hsi Lee , Shu-Yi Chen
发明人： Tsung-Hsi Lee , Shu-Yi Chen
IPC分类号： G06F3/041 , G06F3/043 , G06F3/042
CPC分类号： G06F1/1692 , G06F3/0488
摘要： A method for controlling an electronic apparatus including a touchless interface and a control interface, comprising: detecting a first control action applied to the touchless interface; detecting a second control action applied to the control interface; and controlling the electronic apparatus to perform a corresponding function according to the first control action and the second control action.
摘要翻译：一种用于控制包括无接触接口和控制接口的电子设备的方法，包括：检测应用于所述无接触接口的第一控制动作; 检测应用于所述控制接口的第二控制动作; 以及根据第一控制动作和第二控制动作控制电子装置执行对应的功能。

4. 发明申请

US20110113183A1 Method for Managing a Non-Violate Memory and Computer Readable Medium Thereof 有权
标题翻译：用于管理非违规内存和计算机可读介质的方法
公开(公告)号：US20110113183A1
公开(公告)日：2011-05-12
申请号：US12614544
申请日：2009-11-09
申请人： Tsung-Hsi Lee , Wen-Jun Zeng , Chung-Ning Huang , Shin-Hui Huang
发明人： Tsung-Hsi Lee , Wen-Jun Zeng , Chung-Ning Huang , Shin-Hui Huang
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A method for managing a non-violate memory is provided. The non-violate memory has a number of blocks, and each block has a number of sub-blocks. The method includes a number of steps. First, a last physical address is obtained. The last physical address corresponds to a sub-block which is close to another sub-block where data is newly stored. Next, it is determined, for each sub-block of at least one block, the validity of data being stored. The at least one block is at least one neighboring block of a block containing the corresponding sub-block of the last physical address. Then, a mapping table is produced according to the step of determining the validity of data.
摘要翻译：提供了一种用于管理非违规存储器的方法。非违规存储器具有多个块，并且每个块具有多个子块。该方法包括多个步骤。首先，获得最后一个物理地址。最后一个物理地址对应于接近新存储数据的另一子块的子块。接下来，对于至少一个块的每个子块确定正在存储的数据的有效性。至少一个块是包含最后物理地址的对应子块的块的至少一个相邻块。然后，根据确定数据的有效性的步骤产生映射表。

5. 发明授权

US08296506B2 Method for managing a non-violate memory and computer readable medium thereof 有权
标题翻译：用于管理非违规存储器的方法及其计算机可读介质
公开(公告)号：US08296506B2
公开(公告)日：2012-10-23
申请号：US12614544
申请日：2009-11-09
申请人： Tsung-Hsi Lee , Wen-Jun Zeng , Chung-Ning Huang , Shin-Hui Huang
发明人： Tsung-Hsi Lee , Wen-Jun Zeng , Chung-Ning Huang , Shin-Hui Huang
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7201
摘要： A method for managing a non-volatile memory is provided. The non-volatile memory has a number of blocks, and each block has a number of sub-blocks. The method includes a number of steps. First, a last physical address is obtained. The last physical address corresponds to a sub-block which is close to another sub-block where data is newly stored. Next, it is determined, for each sub-block of at least one block, the validity of data being stored. The at least one block is at least one neighboring block of a block containing the corresponding sub-block of the last physical address. Then, a mapping table is produced according to the step of determining the validity of data.
摘要翻译：提供了一种用于管理非易失性存储器的方法。非易失性存储器具有多个块，并且每个块具有多个子块。该方法包括多个步骤。首先，获得最后一个物理地址。最后一个物理地址对应于接近新存储数据的另一子块的子块。接下来，对于至少一个块的每个子块确定正在存储的数据的有效性。至少一个块是包含最后物理地址的对应子块的块的至少一个相邻块。然后，根据确定数据的有效性的步骤产生映射表。

6. 发明授权

US07880629B2 Power supply device 有权
标题翻译：电源设备
公开(公告)号：US07880629B2
公开(公告)日：2011-02-01
申请号：US12329606
申请日：2008-12-07
申请人： Tsung-Hsi Lee
发明人： Tsung-Hsi Lee
IPC分类号： G08B21/00
CPC分类号： H02H3/046 , H02H3/087
摘要： A power supply device for supplying power to a communication device includes a power source, a first fuse, a second fuse, a voltage converter, a photo coupler, and a central processing unit (CPU). The voltage converter is configured for receiving first power signals from the power source via the first fuse and the second fuse, and converting the first power signals to second power signals. The photo coupler connected in parallel to the third resistor, configured for outputting a first electrical signal upon the condition that the first fuse and the second fuse are operational, and outputting a second electrical signal upon the condition that at least one of the first fuse and the second fuse is blown. The CPU is connected to the photo coupler, configured for generating an alarm message upon receiving the second electrical signal from the photo coupler.
摘要翻译：用于向通信设备供电的电源设备包括电源，第一保险丝，第二保险丝，电压转换器，光耦合器和中央处理单元（CPU）。电压转换器被配置为经由第一熔丝和第二熔丝从电源接收第一功率信号，并将第一功率信号转换为第二功率信号。与第三电阻并联连接的光耦合器，被配置为在第一熔丝和第二熔丝运行的情况下输出第一电信号，并且在第一熔丝和第二个保险丝熔断。 CPU连接到光耦合器，用于在从光耦合器接收到第二电信号时产生报警消息。

7. 发明授权

US08381007B2 Data storage system with power backup mechanism 有权
标题翻译：数据存储系统具备电源备份机制
公开(公告)号：US08381007B2
公开(公告)日：2013-02-19
申请号：US12846852
申请日：2010-07-30
申请人： Sio-Pang Chan , Tsung-Hsi Lee
发明人： Sio-Pang Chan , Tsung-Hsi Lee
IPC分类号： G06F1/28
CPC分类号： G06F1/28 , G06F11/2015
摘要： A data storage system with power backup mechanism includes a storage server, N pieces of power supply modules, a plurality of programmable logic devices and a control module. The storage server consumes M units of power in operation, and supports a storage bridge bay standard. The power supply modules respectively generate power for the storage server and a set of power-related signals, wherein the maximum power output of each of the power supply modules is equal to M/N−1 units. The programmable logic devices convert the power-related signals from the power supply modules to two sets of power condition signals. The control module monitors a power condition according to the power condition signals, thereby determining a power health condition of the storage server.
摘要翻译：具有备电机构的数据存储系统包括存储服务器，N个电源模块，多个可编程逻辑设备和控制模块。存储服务器在运行时消耗M个电源单元，并支持存储桥接桥标准。电源模块分别为存储服务器产生电力和一组功率相关信号，其中每个电源模块的最大功率输出等于M / N-1个单元。可编程逻辑器件将来自电源模块的功率相关信号转换为两组电源条件信号。控制模块根据功率状态信号监视电力状况，从而确定存储服务器的功率健康状况。

8. 发明申请

US20110116325A1 COMPUTER APPARATUS AND MEMORY ERROR SIGNAL DETECTING SYSTEM 有权
标题翻译：计算机装置和存储器错误信号检测系统
公开(公告)号：US20110116325A1
公开(公告)日：2011-05-19
申请号：US12759345
申请日：2010-04-13
申请人： Tsung-Hsi Lee
发明人： Tsung-Hsi Lee
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G06F11/0751 , G06F11/073
摘要： A memory error signal detecting system including a signal extracting circuit, a flip-flop, a latch circuit, and a light sign is provided. The signal extracting circuit receives a memory error signal to output a pulse signal when the memory error signal switches from a first level to a second level. When the preset end of the flip-flop receives the pulse signal, and the maintaining time of the pulse signal is maintained for a predetermine time, the flip-flop output end is set to a high voltage level. The latch circuit determines whether to output the state of the flip-flop output according to the reset signal. The light sign operates according to the state of an output end of the latch circuit. Furthermore, a computer apparatus including the memory error signal detecting system is also provided.
摘要翻译：提供了包括信号提取电路，触发器，锁存电路和光标志的存储器误差信号检测系统。当存储器误差信号从第一电平切换到第二电平时，信号提取电路接收存储器误差信号以输出脉冲信号。当触发器的预设端接收到脉冲信号，并且脉冲信号的保持时间保持预定时间时，触发器输出端被设置为高电压电平。锁存电路根据复位信号确定是否输出触发器输出的状态。光符号根据锁存电路的输出端的状态来工作。此外，还提供了包括存储器错误信号检测系统的计算机装置。

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