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1. 发明授权

US06537914B1 Integrated circuit device isolation methods using high selectivity chemical-mechanical polishing 有权
标题翻译：集成电路器件隔离方法采用高选择性化学机械抛光
公开(公告)号：US06537914B1
公开(公告)日：2003-03-25
申请号：US09570225
申请日：2000-05-12
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee , Jung-yup Kim , Chang-ki Hong , Ho-kyu Kang
IPC分类号： H01L21302
CPC分类号： C09G1/02 , C09K3/1463 , H01L21/31053 , H01L21/76224
摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.
摘要翻译：用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。特别地，蚀刻衬底表面以形成沟槽。然后在衬底表面和沟槽中形成绝缘层。绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

2. 发明授权

US06465866B2 Trench isolation regions having trench liners with recessed ends 有权
标题翻译：具有凹槽端的沟槽衬套的沟槽隔离区
公开(公告)号：US06465866B2
公开(公告)日：2002-10-15
申请号：US09911096
申请日：2001-07-23
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

3. 发明授权

US06331469B1 Trench isolation structure, semiconductor device having the same, and trench isolation method 有权
标题翻译：沟槽隔离结构，具有相同的半导体器件，以及沟槽隔离方法
公开(公告)号：US06331469B1
公开(公告)日：2001-12-18
申请号：US09684822
申请日：2000-10-10
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

4. 发明授权

US06258726B1 Method of forming isolation film for semiconductor devices 失效
标题翻译：形成半导体器件隔离膜的方法
公开(公告)号：US06258726B1
公开(公告)日：2001-07-10
申请号：US09412888
申请日：1999-10-05
申请人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
发明人： Tai-Su Park , Yu-gyun Shin , Han-sin Lee , Kyung-won Park
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.
摘要翻译：形成隔离膜的方法形成用于将有源区域的边缘连接到隔离膜的间隔物。间隔物位于沟槽的上侧壁上，并平滑了隔离膜的电平与有源区的电平之间的转变或台阶。因此，可以在随后的工艺中在整个有源区上形成均匀厚度的栅极氧化膜，从而防止栅极氧化膜的特性劣化。间隔物可以使用用于形成沟槽的硬掩模上的侧壁间隔物形成。侧壁间隔件保护形成在沟槽中的隔离部分，并且在去除侧壁间隔物之后的蚀刻可围绕被保护部分以形成隔离物。此外，为了消除隔离膜中的应力和缺陷，隔离膜的致密化退火可以在诸如约1150℃的高温下进行，因为间隔物减轻了隔离膜的收缩或下垂的影响。

5. 发明授权

US5858858A Annealing methods for forming isolation trenches 失效
标题翻译：用于形成隔离沟的退火方法
公开(公告)号：US5858858A
公开(公告)日：1999-01-12
申请号：US729453
申请日：1996-10-11
申请人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.
摘要翻译：一种形成微电子结构的方法包括以下步骤：在衬底上形成掩模层，在衬底的暴露部分形成沟槽，形成填充沟槽并覆盖掩模层的绝缘材料层，并退火绝缘材料在至少约1150℃的温度下进行。退火步骤可以进行约0.5小时至约8小时的时间，退火步骤可以在惰性气氛中进行。

6. 发明授权

US6121110A Trench isolation method for semiconductor device 失效
标题翻译：半导体器件的沟槽隔离方法
公开(公告)号：US6121110A
公开(公告)日：2000-09-19
申请号：US124093
申请日：1998-07-29
申请人： Soo-jin Hong , Yu-gyun Shin , Han-sin Lee , Hyun-cheol Choe
发明人： Soo-jin Hong , Yu-gyun Shin , Han-sin Lee , Hyun-cheol Choe
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.
摘要翻译：提供沟槽隔离方法。在沟槽隔离方法中，顺序地在半导体衬底上形成衬垫氧化膜，氧化膜和蚀刻掩模膜，然后在半导体衬底的场区域中形成沟槽。通过氧化半导体衬底，在沟槽的内壁和氧化膜的侧壁上形成氧化膜。在用电介质材料填充沟槽之后，去除在活性区域中形成的衬垫氧化膜，氧化膜和蚀刻掩模膜。

7. 发明授权

US06436611B1 Trench isolation method for semiconductor integrated circuit 有权
标题翻译：半导体集成电路沟槽隔离方法
公开(公告)号：US06436611B1
公开(公告)日：2002-08-20
申请号：US09611799
申请日：2000-07-07
申请人： Han-sin Lee
发明人： Han-sin Lee
IPC分类号： G03F700
CPC分类号： H01L21/76229
摘要： A trench isolation method of a semiconductor integrated circuit is provided. In the trench isolation method, a mask pattern which defines a first opening and a second opening wider than the first opening is formed on a semiconductor substrate. A first spacer for filling the first opening and a second spacer are formed at the sidewalls of the second opening. A sacrificial material layer pattern having an etching rate substantially equal to that of the semiconductor substrate is formed in the second opening surrounded by the second spacer. The semiconductor substrate under the first and second spacers is exposed by selectively removing the first and second spacers. A deep trench region and a shallow trench region are formed in the exposed semiconductor substrate and under the sacrificial material layer, respectively, by etching the exposed semiconductor substrate and the sacrificial material layer pattern. An isolation layer filling the deep trench region and the shallow trench region is formed.
摘要翻译：提供半导体集成电路的沟槽隔离方法。在沟槽隔离方法中，在半导体衬底上形成限定第一开口和比第一开口宽的第二开口的掩模图案。用于填充第一开口的第一间隔件和第二间隔件形成在第二开口的侧壁处。在由第二间隔物包围的第二开口中形成具有与半导体衬底的蚀刻速率基本相等的蚀刻速率的牺牲材料层图案。通过选择性地去除第一和第二间隔物来暴露第一和第二间隔物下的半导体衬底。通过蚀刻暴露的半导体衬底和牺牲材料层图案，分别在暴露的半导体衬底中和牺牲材料层下面形成深沟槽区域和浅沟槽区域。形成了填充深沟槽区域和浅沟槽区域的隔离层。

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