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1. 发明授权

US07471099B2 Semiconductor device with mechanism for leak defect detection 有权
标题翻译：具有泄漏缺陷检测机制的半导体器件
公开(公告)号：US07471099B2
公开(公告)日：2008-12-30
申请号：US11085144
申请日：2005-03-22
申请人： Yuji Kurita , Hiroyoshi Yamashita , Hitoaki Nishiwaki
发明人： Yuji Kurita , Hiroyoshi Yamashita , Hitoaki Nishiwaki
IPC分类号： G01R31/02
CPC分类号： G01R31/3008 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2924/20753 , H01L2924/20754 , H01L2924/00012
摘要： A semiconductor device includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.
摘要翻译：半导体器件包括多个信号端子，第一电源端子，第二电源端子，耦合到多个信号端子的核心电路和第一电源端子，耦合在各个信号端子之间的多个第一晶体管和第二电源端子，以及耦合在各个信号端子和接地电位之间的多个第二晶体管，其中，所述核心电路被配置为使所述第一晶体管交替地导通和不导电，并且使得所述第二晶体管不导通并且在使得第一晶体管和第二晶体管中的一个相对于给定的信号端子导通，使得第一晶体管和第二晶体管中的另一个相对于给定的信号端子不导通。

2. 发明申请

US20050235069A1 Microcontroller 审中-公开
标题翻译：微控制器
公开(公告)号：US20050235069A1
公开(公告)日：2005-10-20
申请号：US10949300
申请日：2004-09-27
申请人： Hirokazu Miwa , Yasuyuki Hori , Hiroyoshi Yamashita
发明人： Hirokazu Miwa , Yasuyuki Hori , Hiroyoshi Yamashita
IPC分类号： G06F15/78 , G06F13/14 , G06F13/40
CPC分类号： G06F13/4072
摘要： An external port control register of an input/output port outputs a setting value signal indicating a setting value in order that either a general-purpose input/output port function or a functional block input/output pin function is set to an external pin. A selector of the input/output port connects either a general output path or an output path of a functional block receiving a functional block input signal, to the external pin according to the setting value signal. An interrupting circuit interrupts the supply of the functional block input signal to the functional block when the setting value signal indicates the general-purpose input/output port function. Consequently, any register circuit designating whether to enable or disable the supply of the functional block input signal to the functional block need not be provided in particular, which can eliminate the need for a redundant setting process in switching the pin function of the external pin.
摘要翻译：输入/输出端口的外部端口控制寄存器输出指示设定值的设定值信号，以便将通用输入/输出端口功能或功能块输入/输出引脚功能设置为外部引脚。输入/输出端口的选择器根据设置值信号将接收功能块输入信号的功能块的通用输出路径或输出路径连接到外部引脚。当设定值信号表示通用输入/输出端口功能时，中断电路中断向功能块提供功能块输入信号。因此，不需要特别提供指定是否启用功能块输入信号供给功能块的任何寄存器电路，这样可以消除在切换外部引脚的引脚功能时的冗余设置处理的需要。

3. 发明授权

US06653871B2 Method of and circuit for controlling a clock 有权
标题翻译：控制时钟的方法和电路
公开(公告)号：US06653871B2
公开(公告)日：2003-11-25
申请号：US10073490
申请日：2002-02-13
申请人： Masashi Masuda , Hiroyoshi Yamashita , Akio Hara , Kohji Kitagawa
发明人： Masashi Masuda , Hiroyoshi Yamashita , Akio Hara , Kohji Kitagawa
IPC分类号： H03K1700
CPC分类号： G06F1/324 , G06F1/08 , G06F1/3203 , Y02D10/126
摘要： This invention relates to switching-over to a higher speed clock from a lower speed clock. The switching-over of the clock is performed before, after, or simultaneously to a transition to a sleep mode is carried out. After the switching-over of the clock is performed, if oscillation of the high speed clock and an internal voltage are stabilized, it is returned to a normal mode from the sleep mode.
摘要翻译：本发明涉及从较低速时钟切换到较高速时钟。在执行到睡眠模式的转换之前，之后或同时执行时钟的切换。执行时钟切换后，如果高速时钟的振荡和内部电压稳定，则从睡眠模式返回到正常模式。

4. 发明授权

US08588743B2 Communication device and communication system 有权
标题翻译：通信设备和通信系统
公开(公告)号：US08588743B2
公开(公告)日：2013-11-19
申请号：US11798304
申请日：2007-05-11
申请人： Hiroyoshi Yamashita , Hiroyuki Fujiyama
发明人： Hiroyoshi Yamashita , Hiroyuki Fujiyama
IPC分类号： H04M1/66
CPC分类号： H04W12/06 , H04W74/0866 , H04W88/18
摘要： A communication device capable of preventing interference due to collision of signals of a plurality of communication devices (slaves) is provided. The communication device characterized by having a receiving part which receives a request signal by radio, a counter which starts count of a count value on reception of the request signal, a comparing part which compares the count value and a comparison value, and a transmitting part which transmits an acknowledge signal by radio in accordance with a result of the comparison is provided.
摘要翻译：提供能够防止由于多个通信设备（从站）的信号的冲突引起的干扰的通信设备。所述通信装置的特征在于，具有通过无线电接收请求信号的接收部，开始接收请求信号时的计数值的计数的计数器，比较计数值和比较值的比较部，以及发送部提供了根据比较结果通过无线电发送确认信号的装置。

5. 发明申请

US20060139822A1 Semiconductor device with mechanism for leak defect detection 有权
标题翻译：具有泄漏缺陷检测机制的半导体器件
公开(公告)号：US20060139822A1
公开(公告)日：2006-06-29
申请号：US11085144
申请日：2005-03-22
申请人： Yuji Kurita , Hiroyoshi Yamashita , Hitoaki Nishiwaki
发明人： Yuji Kurita , Hiroyoshi Yamashita , Hitoaki Nishiwaki
IPC分类号： H02H9/00
CPC分类号： G01R31/3008 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2924/20753 , H01L2924/20754 , H01L2924/00012
摘要： A semiconductor device includes a plurality of signal terminals, a first power supply terminal, a second power supply terminal, a core circuit coupled to the plurality of signal terminals and the first power supply terminal, a plurality of first transistors coupled between the respective signal terminals and the second power supply terminal, and a plurality of second transistors coupled between the respective signal terminals and a ground potential, wherein the core circuit is configured to make the first transistors conductive and nonconductive alternately and make the second transistors nonconductive and conductive alternately at a time of test operation, such that one of a first transistor and a second transistor being conductive with respect to a given signal terminal requires another one of the first transistor and the second transistor to be nonconductive with respect to the given signal terminal.
摘要翻译：半导体器件包括多个信号端子，第一电源端子，第二电源端子，耦合到多个信号端子的核心电路和第一电源端子，耦合在各个信号端子之间的多个第一晶体管和第二电源端子，以及耦合在各个信号端子和接地电位之间的多个第二晶体管，其中，所述核心电路被配置为使所述第一晶体管交替地导通和不导电，并且使得所述第二晶体管不导通并且在使得第一晶体管和第二晶体管中的一个相对于给定的信号端子导通，使得第一晶体管和第二晶体管中的另一个相对于给定的信号端子不导通。

6. 发明授权

US06516378B1 Microprocessor for controlling busses 有权
标题翻译：用于控制总线的微处理器
公开(公告)号：US06516378B1
公开(公告)日：2003-02-04
申请号：US09426757
申请日：1999-10-26
申请人： Hiroyoshi Yamashita , Masaaki Tani
发明人： Hiroyoshi Yamashita , Masaaki Tani
IPC分类号： G06F1342
CPC分类号： G06F13/4022
摘要： The present invention provides a microprocessor capable of improving the throughput of a CPU. Module like the program ROMs in which instruction accesses are concentrated by a CPU are put together in a first Princeton bus, and modules like the external bus I/F, SDRAM I/F, peripheral bus I/F in which data accesses are mainly concentrated are put together in a second Princeton bus. Therefore, the instruction access and the data access can be carried out in parallel with respect to the buses of the instruction bus and the data bus individually through a bus control unit. Because the buses can be used efficiently, the throughput of the CPU can be improved substantially.
摘要翻译：本发明提供一种能够提高CPU的吞吐量的微处理器。类似于其中指令访问由CPU集中的程序ROM的模块在第一个普林斯顿总线中放在一起，而外部总线I / F，SDRAM I / F，数据访问的外设总线I / F等模块主要集中在在第二条普林斯顿公共汽车上放在一起。因此，可以通过总线控制单元分别对指令总线和数据总线的总线进行并行执行指令访问和数据访问。由于可以有效地使用总线，所以可以大幅提高CPU的吞吐量。

7. 发明申请

US20080064368A1 Communication device and communication system 有权
标题翻译：通信设备和通信系统
公开(公告)号：US20080064368A1
公开(公告)日：2008-03-13
申请号：US11798304
申请日：2007-05-11
申请人： Hiroyoshi Yamashita , Hiroyuki Fujiyama
发明人： Hiroyoshi Yamashita , Hiroyuki Fujiyama
IPC分类号： H04M1/66
CPC分类号： H04W12/06 , H04W74/0866 , H04W88/18
摘要： A communication device capable of preventing interference due to collision of signals of a plurality of communication devices (slaves) is provided. The communication device characterized by having a receiving part which receives a request signal by radio, a counter which starts count of a count value on reception of the request signal, a comparing part which compares the count value and a comparison value, and a transmitting part which transmits an acknowledge signal by radio in accordance with a result of the comparison is provided.
摘要翻译：提供能够防止由于多个通信设备（从站）的信号的冲突引起的干扰的通信设备。所述通信装置的特征在于，具有通过无线电接收请求信号的接收部，开始接收请求信号时的计数值的计数的计数器，比较计数值和比较值的比较部，以及发送部提供了根据比较结果通过无线电发送确认信号的装置。

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