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1. 发明申请

WO2010145482A1 APPARATUS AND METHOD FOR CLASS-G LINE DRIVER CONTROL SIGNAL 审中-公开
标题翻译：用于类别G线驱动器控制信号的装置和方法
公开(公告)号：WO2010145482A1
公开(公告)日：2010-12-23
申请号：PCT/CN2010/073693
申请日：2010-06-09
申请人： HUAWEI TECHNOLOGIES CO., LTD. , HESSAM, Mohajeri , AMIR, H. Fazlollahi
发明人： HESSAM, Mohajeri , AMIR, H. Fazlollahi
IPC分类号： H03F1/02
CPC分类号： H03F1/025 , H03F3/21 , H03F2200/504 , H03F2200/507 , H03F2200/511 , H03H11/18 , H04L25/0286 , H04L25/03019 , H04L25/03343 , H04L25/03885 , Y10T307/696
摘要： An apparatus comprising an input, a control signal generator coupled to the input and having a control signal generator output, and an amplifier coupled to the control signal generator output, wherein a voltage supplied to the amplifier is switched based on the control signal generator output, and wherein the control signal generator output is based on a data signal in the input. Also included is an apparatus comprising circuitry configured to implement a method comprising detecting an incoming signal, calculating a derivative of the incoming signal, estimating a future incoming signal based on the derivative of the incoming signal and a time step, and providing the estimated future incoming signal to switch between a first supply voltage and a second supply voltage prior to or concurrent with an arrival of the future incoming signal at the switch, wherein the incoming signal and the future incoming signal are analog signals.
摘要翻译：一种装置，包括输入端，耦合到输入端并具有控制信号发生器输出端的控制信号发生器和耦合到控制信号发生器输出端的放大器，其中基于控制信号发生器输出切换提供给放大器的电压，并且其中所述控制信号发生器输出基于所述输入中的数据信号。还包括一种装置，其包括被配置为实现一种方法的电路，该方法包括检测输入信号，计算输入信号的导数，基于输入信号的导数和时间步长来估计未来输入信号，以及提供估计的未来进入信号在开关之前或未来的进入信号的到达之前在第一电源电压和第二电源电压之间切换，其中输入信号和未来的输入信号是模拟信号。

2. 发明授权

US06728368B1 Apparatus and method for a highly efficient low power driver for a central office ADSL system 失效
公开(公告)号：US06728368B1
公开(公告)日：2004-04-27
申请号：US09707570
申请日：2000-11-06
申请人： Hessam Mohajeri
发明人： Hessam Mohajeri
IPC分类号： H04M100
CPC分类号： H04L27/0002 , H04L27/2626 , H04M3/005
摘要： An apparatus and method to implement a highly efficient low power line driver. In a first embodiment, the invention provides a method to increase the power efficiency of a line driver. The method includes supplying a digital signal processor output to a first subtractor; supplying the first subtractor output as an input to a modulator of a line driver; subtracting the line driver output from the digital signal processor output at the first subtractor; filtering the line driver output with a low pass filter; routing the line driver output to an impedance match filter; providing a first analog-to-digital converter and a second subtractor to subtract the line impedance match filter output from the low pass filter output; providing a digital filter and a second analog-to-digital converter; and subtracting the digital filter output from the first analog-to-digital converter output at a third subtractor to output a feedback signal to the digital signal processor. In a second embodiment, the invention provides an ADSL system with a line driver. The system line driver includes a first subtractor; a digital signal processor to supply a signal to the first subtractor; a line driver receiving an input from the first subtractor, wherein a first closed loop path is provided from the line driver output to the first subtractor; a line impedance match filter receiving the line driver output as an input; a low pass filter, receiving the line driver output as an input; a second subtractor circuit to subtract the line impedance match filter output from the low pass filter output, wherein the second subtractor provides an input to a first analog-to-digital converter; a second analog-to-digital converter; a digital filter to receive an input from the second analog-to-digital converter; and a third subtractor to subtract the digital filter output from the first analog-to-digital converter output, wherein the third subtractor produces a feedback input signal to the digital signal processor.

3. 发明授权

US5875235A Transformerless data access arrangement 失效
标题翻译：无变压器数据存取安排
公开(公告)号：US5875235A
公开(公告)日：1999-02-23
申请号：US813343
申请日：1997-03-07
申请人： Hessam Mohajeri
发明人： Hessam Mohajeri
IPC分类号： H04M1/57 , H04M11/06 , H04M11/00
CPC分类号： H04M11/06 , H04M1/57
摘要： A transformerless data access arrangement (DAA) device facilitates data transfer between a high speed modem device and a central office telephone line (i.e., a phone line). The DAA device uses D/A and A/D converters in conjunction with a pair of nonlinear opto-couplers that function as an isolation barrier. The A/D converter converts an analog signal received from the phone line into a one-bit modulated digital signal. The digital signal is relayed by the nonlinear opto-couplers to a processor. Since the relayed signal is digital, the use of nonlinear opto-couplers does not result in unacceptable levels of noise and distortion. This is relevant since high speed modems have stringent noise and distortion requirements. A phone line supply voltage is regulated internally and used to power the DAA device. When the processor detects a ring signal on the phone line, the processor generates a control signal which places the A/D and D/A converters in idle mode while sending a caller ID directly to the processor. The processor also initiates a control signal to place the DAA device in and out of its normal operation mode if an off-hook condition is detected.
摘要翻译：无变压器数据访问装置（DAA）装置便于高速调制解调器装置和中心局电话线（即电话线）之间的数据传送。 DAA设备使用D / A和A / D转换器与一对用作隔离屏障的非线性光耦合器。 A / D转换器将从电话线接收的模拟信号转换为一位调制数字信号。数字信号由非线性光耦合器中继到处理器。由于中继信号是数字的，所以使用非线性光耦合器不会导致不可接受的噪声和失真水平。这是相关的，因为高速调制解调器具有严格的噪声和失真要求。电话线电源电压在内部进行调节，用于为DAA设备供电。当处理器检测到电话线路上的振铃信号时，处理器产生控制信号，将A / D和D / A转换器置于空闲模式，同时将呼叫者ID直接发送到处理器。如果检测到摘机状态，则处理器还启动控制信号以将DAA设备放入和退出其正常操作模式。

4. 发明授权

US09203418B2 Phase locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US09203418B2
公开(公告)日：2015-12-01
申请号：US14244400
申请日：2014-04-03
申请人： Hessam Mohajeri , Bruno Tourette
发明人： Hessam Mohajeri , Bruno Tourette
IPC分类号： H03L7/06 , H03L7/107 , H03L7/081 , H03L7/197 , H03L7/23
CPC分类号： H03L7/1075 , H03L7/0814 , H03L7/1976 , H03L7/235
摘要： The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.
摘要翻译：本公开提供了一种时钟发生器电路，包括被配置为产生主时钟信号的主时钟发生器单元和多个从锁相环单元。多个从相循环单元中的每一个被配置为接收主时钟信号作为输入参考信号和对应的源时钟信号。从动锁相环单元可以包括内环和外环。内环可以包括锁定在从主时钟发生器单元接收的主时钟信号上的频率合成器，而外环可以包括二进制相位检测器，其输出到具有比例和积分作用的环路滤波器，控制内环频率值通过Σ-Δ输入。

5. 发明申请

US20100321115A1 Class-G Line Driver Control Signal 有权
标题翻译： G类线路驱动控制信号
公开(公告)号：US20100321115A1
公开(公告)日：2010-12-23
申请号：US12697913
申请日：2010-02-01
申请人： Hessam Mohajeri , Amir H. Fazlollahi
发明人： Hessam Mohajeri , Amir H. Fazlollahi
IPC分类号： H03F3/04 , H02J1/00 , H03L7/00
CPC分类号： H03F1/025 , H03F3/21 , H03F2200/504 , H03F2200/507 , H03F2200/511 , H03H11/18 , H04L25/0286 , H04L25/03019 , H04L25/03343 , H04L25/03885 , Y10T307/696
摘要： An apparatus comprising an input, a control signal generator coupled to the input and having a control signal generator output, and an amplifier coupled to the control signal generator output, wherein a voltage supplied to the amplifier is switched based on the control signal generator output, and wherein the control signal generator output is based on a data signal in the input. Also included is an apparatus comprising circuitry configured to implement a method comprising detecting an incoming signal, calculating a derivative of the incoming signal, estimating a future incoming signal based on the derivative of the incoming signal and a time step, and providing the estimated future incoming signal to switch between a first supply voltage and a second supply voltage prior to or concurrent with an arrival of the future incoming signal at the switch, wherein the incoming signal and the future incoming signal are analog signals.
摘要翻译：一种装置，包括输入端，耦合到输入端并具有控制信号发生器输出端的控制信号发生器和耦合到控制信号发生器输出端的放大器，其中基于控制信号发生器输出切换提供给放大器的电压，并且其中所述控制信号发生器输出基于所述输入中的数据信号。还包括一种装置，其包括被配置为实现一种方法的电路，该方法包括检测输入信号，计算输入信号的导数，基于输入信号的导数和时间步长来估计未来输入信号，以及提供估计的未来进入信号在开关之前或未来的进入信号的到达之前在第一电源电压和第二电源电压之间切换，其中输入信号和未来的输入信号是模拟信号。

6. 发明授权

US06850618B1 Central office interface techniques for digital subscriber lines 有权
标题翻译：数字用户线的中心局接口技术
公开(公告)号：US06850618B1
公开(公告)日：2005-02-01
申请号：US09570804
申请日：2000-05-15
申请人： Hessam Mohajeri , Serdar Kiykioglu , Heron Babaei
发明人： Hessam Mohajeri , Serdar Kiykioglu , Heron Babaei
IPC分类号： H04M11/06 , H04M1/00 , H04M9/00
CPC分类号： H04M11/062
摘要： A splitterless interface between a digital subscriber line (DSL) and the central office equipment that can receive and isolate the low frequency voice data and high frequency digital data from a telephone line. This interface can also mix and transmit low frequency voice data and high frequency digital data onto a telephone line. For POTS band frequencies, a reactive impedance coupled across the two-wire interface of the POTS line card, and serially coupled to the line side of the DSL coupling transformer, has an open state magnitude. The magnitude of the line side windings of the DSL coupling transformer is low at POTS band frequencies. POTS band signal power is therefore delivered to the POTS line card. For DSL band frequencies, the reactive impedance across the two-wire interface of the POTS line card has a closed state magnitude. The POTS line card is therefore essentially short-circuited at DSL band frequencies, and DSL band signal power is delivered to the DSL modem. The frequency band in which the reactive impedance transitions from an open state magnitude to a closed state magnitude corresponds to the frequency band between the POTS frequency band and the DSL frequency band.
摘要翻译：数字用户线（DSL）与中心局设备之间的无分离器接口，可以从电话线接收和隔离低频语音数据和高频数字数据。该接口还可以将低频语音数据和高频数字数据混合并传输到电话线上。对于POTS频带频率，耦合在POTS线卡的两线接口上并串联耦合到DSL耦合变压器的线路侧的无功阻抗具有开放状态幅度。 DSL耦合变压器的线路侧绕组的幅度在POTS频带频率较低。因此，POTS频带信号功率被传送到POTS线路卡。对于DSL频段，POTS线卡两线接口之间的无功阻抗具有闭合状态幅度。因此，POTS线卡在DSL频带频率基本上短路，并且DSL频带信号功率被传送到DSL调制解调器。其中无功阻抗从开态状态幅度转变到闭状态幅度的频带对应于POTS频带和DSL频带之间的频带。

7. 发明申请

US20130300470A1 Low Jitter Clock Generator for Multiple Lanes High Speed Data Transmitter 失效
标题翻译：用于多通道的低抖动时钟发生器高速数据发送器
公开(公告)号：US20130300470A1
公开(公告)日：2013-11-14
申请号：US13829759
申请日：2013-03-14
申请人： Hessam Mohajeri , Bruno Tourette
发明人： Hessam Mohajeri , Bruno Tourette
IPC分类号： H03L7/107
CPC分类号： H03L7/1075 , H03L7/0814 , H03L7/1976 , H03L7/235
摘要： The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.
摘要翻译：本公开提供了一种时钟发生器电路，包括被配置为产生主时钟信号的主时钟发生器单元和多个从锁相环单元。多个从相循环单元中的每一个被配置为接收主时钟信号作为输入参考信号和对应的源时钟信号。从动锁相环单元可以包括内环和外环。内环可以包括锁定在从主时钟发生器单元接收的主时钟信号上的频率合成器，而外环可以包括二进制相位检测器，其输出到具有比例和积分作用的环路滤波器，控制内环频率值通过Σ-Δ输入。

8. 发明授权

US08446219B2 Class-G line driver control signal 有权
标题翻译： Class-G线路驱动控制信号
公开(公告)号：US08446219B2
公开(公告)日：2013-05-21
申请号：US12697913
申请日：2010-02-01
申请人： Hessam Mohajeri , Amir H. Fazlollahi
发明人： Hessam Mohajeri , Amir H. Fazlollahi
IPC分类号： H03F3/20
CPC分类号： H03F1/025 , H03F3/21 , H03F2200/504 , H03F2200/507 , H03F2200/511 , H03H11/18 , H04L25/0286 , H04L25/03019 , H04L25/03343 , H04L25/03885 , Y10T307/696
摘要： An apparatus comprising an input, a control signal generator coupled to the input and having a control signal generator output, and an amplifier coupled to the control signal generator output, wherein a voltage supplied to the amplifier is switched based on the control signal generator output, and wherein the control signal generator output is based on a data signal in the input. Also included is an apparatus comprising circuitry configured to implement a method comprising detecting an incoming signal, calculating a derivative of the incoming signal, estimating a future incoming signal based on the derivative of the incoming signal and a time step, and providing the estimated future incoming signal to switch between a first supply voltage and a second supply voltage prior to or concurrent with an arrival of the future incoming signal at the switch, wherein the incoming signal and the future incoming signal are analog signals.
摘要翻译：一种装置，包括输入端，耦合到输入端并具有控制信号发生器输出端的控制信号发生器和耦合到控制信号发生器输出端的放大器，其中基于控制信号发生器输出切换提供给放大器的电压，并且其中所述控制信号发生器输出基于所述输入中的数据信号。还包括一种装置，其包括被配置为实现一种方法的电路，该方法包括检测输入信号，计算输入信号的导数，基于输入信号的导数和时间步长来估计未来输入信号，以及提供估计的未来进入信号在开关之前或未来的进入信号的到达之前在第一电源电压和第二电源电压之间切换，其中输入信号和未来的输入信号是模拟信号。

9. 发明申请

US20140292388A1 PHASE LOCKED LOOP CIRCUIT 审中-公开
标题翻译：相位锁定环路
公开(公告)号：US20140292388A1
公开(公告)日：2014-10-02
申请号：US14244400
申请日：2014-04-03
申请人： Hessam Mohajeri , Bruno Touretta
发明人： Hessam Mohajeri , Bruno Touretta
IPC分类号： H03L7/107
CPC分类号： H03L7/1075 , H03L7/0814 , H03L7/1976 , H03L7/235
摘要： The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.
摘要翻译：本公开提供了一种时钟发生器电路，包括被配置为产生主时钟信号的主时钟发生器单元和多个从锁相环单元。多个从相循环单元中的每一个被配置为接收主时钟信号作为输入参考信号和对应的源时钟信号。从动锁相环单元可以包括内环和外环。内环可以包括锁定在从主时钟发生器单元接收的主时钟信号上的频率合成器，而外环可以包括二进制相位检测器，其输出到具有比例和积分作用的环路滤波器，控制内环频率值通过Σ-Δ输入。

10. 发明授权

US08804888B2 Wide band clock data recovery 有权
标题翻译：宽带时钟数据恢复
公开(公告)号：US08804888B2
公开(公告)日：2014-08-12
申请号：US13180453
申请日：2011-07-11
申请人： Hessam Mohajeri , Bruno Tourette , Emad Afifi
发明人： Hessam Mohajeri , Bruno Tourette , Emad Afifi
IPC分类号： H04L7/00
CPC分类号： H03L7/06 , H03L7/087 , H04L7/0025 , H04L7/033
摘要： The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.
摘要翻译：本公开提供了一种时钟数据恢复电路，其包括锁相环单元，延迟锁定环单元和数字时钟数据恢复单元。锁相环单元基于参考信号产生时钟信号。延迟锁定环单元从锁相环接收时钟信号，将时钟信号分为多个时钟信号并输出时钟信号。数字时钟数据恢复单元接收输入电流信号，估计输入电流信号的频率，输出可以发送到锁相环单元的具有频率的参考信号，从延迟锁定环接收时钟信号，基于时钟信号对输入电流信号的相位进行调整，并输出对准的电流信号。

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