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1. 发明申请

US20140292388A1 PHASE LOCKED LOOP CIRCUIT 审中-公开
标题翻译：相位锁定环路
公开(公告)号：US20140292388A1
公开(公告)日：2014-10-02
申请号：US14244400
申请日：2014-04-03
申请人： Hessam Mohajeri , Bruno Touretta
发明人： Hessam Mohajeri , Bruno Touretta
IPC分类号： H03L7/107
CPC分类号： H03L7/1075 , H03L7/0814 , H03L7/1976 , H03L7/235
摘要： The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.
摘要翻译：本公开提供了一种时钟发生器电路，包括被配置为产生主时钟信号的主时钟发生器单元和多个从锁相环单元。多个从相循环单元中的每一个被配置为接收主时钟信号作为输入参考信号和对应的源时钟信号。从动锁相环单元可以包括内环和外环。内环可以包括锁定在从主时钟发生器单元接收的主时钟信号上的频率合成器，而外环可以包括二进制相位检测器，其输出到具有比例和积分作用的环路滤波器，控制内环频率值通过Σ-Δ输入。

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