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1. 发明申请

US20050132319A1 Automatic method for routing and designing an LSI 有权
标题翻译：路由和设计LSI的自动方法
公开(公告)号：US20050132319A1
公开(公告)日：2005-06-16
申请号：US10983819
申请日：2004-11-08
申请人： Ulrich Krauch , Juergen Pille , Tobias Werner , Alexander Woerner
发明人： Ulrich Krauch , Juergen Pille , Tobias Werner , Alexander Woerner
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： According to the present invention an automated method is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.
摘要翻译：根据本发明，提供了一种用于布线和设计LSI（大规模集成电路）的自动化方法。首先，要连接的书的实例的至少一个通用性位于芯片上，其中实例的通用是根据所述实例的测量定义的区域。然后，通过根据给定的设计规则优化到相应通用的路由来生成到所述实例的初始路由。因此，针对所述实例确定优化的引脚位置。然后，基于所述优化的引脚位置，生成用于所述实例的布局来代替相应的通用。最后，实际产生的引脚与初始路由的相应末端相连。

2. 发明授权

US5944772A Combined adder and logic unit 失效
标题翻译：组合加法器和逻辑单元
公开(公告)号：US5944772A
公开(公告)日：1999-08-31
申请号：US970076
申请日：1997-11-13
申请人： Juergen Haas , Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
发明人： Juergen Haas , Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
IPC分类号： G06F7/50 , G06F7/575
CPC分类号： G06F7/575 , G06F7/507 , G06F7/508
摘要： A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero. A result selector (70) is controlled by a byte position carry-out signal (Cy55) from the carry network means and by operation control signals to select from the output of said pre-sum logic one of the arithmetic functions (SUM0, SUM1) or one of the logic functions as result of the unit operation.
摘要翻译：组合加法器和逻辑单元具有减小的运算和逻辑运算的运算延迟，并且如果在微处理器芯片的算术和逻辑部分中实现，则提供改进的风扇并降低布线延迟和容量。该单元包括连接到操作数输入的进位网络（30），用于产生字节位置（By0-By7）的进位信号，并且还包括具有位函数发生器（42）的和和逻辑（32）和总和发电机（45,46,48）。所述比特函数发生器从作为逻辑功能输出提供的操作数Ai和Bi比特函数Gi，Pi导出，并作为用于产生预计算函数（SUM0，SUM1）的所述和发生器的输入，以预期一或零的进位信号。结果选择器（70）由来自携带网络装置的字节位置执行输出信号（Cy55）和操作控制信号控制，以从所述算术功能（SUM0，SUM1）之一的所述并行逻辑逻辑的输出中进行选择，或作为单元操作的结果的逻辑功能之一。

3. 发明申请

US20090112963A1 METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD 审中-公开
标题翻译：在二进制算术加法算术单元中执行两个运算符的执行的方法来执行这种方法
公开(公告)号：US20090112963A1
公开(公告)日：2009-04-30
申请号：US11926582
申请日：2007-10-29
申请人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
发明人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
IPC分类号： G06F7/508
CPC分类号： G06F7/507
摘要： A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
摘要翻译：提供电路所在的方法，电路装置和设计结构，以通过将两个操作数细分为相等位数的组来执行二进制运算单元中的两个操作数的减法，通过适当的算术运算生成对分别包含相同比特位置的两个操作数的特定的比特组的中间结果。每个中间结果对的第一个中间结果是在“0”的进位假设下产生的，并且每个中间结果对的第二个中间结果在“1”的进位假设下生成。选择来自每组比特的每个特定中间结果对的正确的中间结果，并且通过适当地合并所选择的正确的中间结果来生成两个操作数的减法的结果。

4. 发明授权

US07401312B2 Automatic method for routing and designing an LSI 有权
标题翻译：路由和设计LSI的自动方法
公开(公告)号：US07401312B2
公开(公告)日：2008-07-15
申请号：US10983819
申请日：2004-11-08
申请人： Ulrich Krauch , Juergen Pille , Tobias Werner , Alexander Woerner
发明人： Ulrich Krauch , Juergen Pille , Tobias Werner , Alexander Woerner
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077
摘要： According to the present invention an automated method is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.
摘要翻译：根据本发明，提供了一种用于布线和设计LSI（大规模集成电路）的自动化方法。首先，要连接的书的实例的至少一个通用性位于芯片上，其中实例的通用是根据所述实例的测量定义的区域。然后，通过根据给定的设计规则优化到相应通用的路由来生成到所述实例的初始路由。因此，针对所述实例确定优化的引脚位置。然后，基于所述优化的引脚位置，生成用于所述实例的布局来代替相应的通用。最后，实际产生的引脚与初始路由的相应末端相连。

5. 发明授权

US06668341B1 Storage cell with integrated soft error detection and correction 失效
标题翻译：具有集成软错误检测和校正的存储单元
公开(公告)号：US06668341B1
公开(公告)日：2003-12-23
申请号：US09689968
申请日：2000-10-12
申请人： Ulrich Krauch , Antje Mueller , Juergen Pille , Dieter Wendel
发明人： Ulrich Krauch , Antje Mueller , Juergen Pille , Dieter Wendel
IPC分类号： G06F1100
CPC分类号： G11C29/74
摘要： Storage devices are presented which have some facility of error indication and error correction. The basic idea of the present invention is to double only the storing part inside the storing cell and share the environmental logic. Especially in case of multi-port cells this reduces the area penalty significantly because the read/write control within the cell is shared and only placed once. Writing the cell always writes both latches so that they hold the same data. A soft error can flip only one of the two latches. Then, a ‘XOR’ block detects that the data is no longer identical. While the data is read out the check bit indicates that the data is corrupted. The approach of doubling only the storing elements can be extended to implement a triple storing element (10, 12, 30) in the same cell. Then, with the help of a small and simple error correction logic (32) in the cell from a ‘majority vote’ can be seen which bit value is wrong in case of a soft error affecting one bit in the cell. Thus, no post-processing is necessary after reading the bit from the cell, as it is true per se. (FIG. 3).
摘要翻译：给出了具有错误指示和错误校正功能的存储设备。本发明的基本思想是将存储单元内的存储部分加倍，并共享环境逻辑。特别是在多端口单元的情况下，由于单元内的读/写控制是共享的，只能放置一次，因此这会大大减少面积损失。写单元格总是写入两个锁存器，以便它们保存相同的数据。软错误只能翻转两个锁存器之一。然后，“异或”块检测到数据不再相同。读出数据时，校验位表示数据已损坏。可以扩展仅存储元件加倍的方法，以在同一单元中实现三重存储元件（10,12,30）。然后，借助于“多数投票”的单元格中的小而简单的纠错逻辑（32），可以看出在单元格中影响一位的软错误的情况下哪个位值是错误的。因此，从单元读取位之后，不需要进行后处理，因为它本身是真实的。（图3）。

6. 发明授权

US5928319A Combined binary/decimal adder unit 失效
标题翻译：组合二进制/十进制加法器单元
公开(公告)号：US5928319A
公开(公告)日：1999-07-27
申请号：US969244
申请日：1997-11-13
申请人： Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
发明人： Wilhelm Haller , Ulrich Krauch , Thomas Ludwig , Holger Wetter
IPC分类号： G06F7/491 , G06F7/50
CPC分类号： G06F7/4912 , G06F7/507
摘要： A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.
摘要翻译：组合的二进制/十进制加法器单元减少了处理二进制编码十进制操作数的操作延迟，并且允许使用组合的二进制/十进制加法单元的处理器单元的增加的周期速率。对于加法器单元的十进制位数的总和的并行生成和分配，对于每个十进制数位置产生预和。预计总和预期小数位置的进位，并且在产生了最高十进制位数的进位信号之后需要进行六次校正。每个十进制位数的进位信号与操作控制信号组合使用，以选择数位位置的正确预置。

7. 发明授权

US08612500B2 Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic 失效
标题翻译：方法和十进制算术逻辑单元结构，产生一个数学的幅度结果
公开(公告)号：US08612500B2
公开(公告)日：2013-12-17
申请号：US12013905
申请日：2008-01-14
申请人： Wilhelm Haller , Ulrich Krauch , Guenter Mayer , Eric M. Schwarz
发明人： Wilhelm Haller , Ulrich Krauch , Guenter Mayer , Eric M. Schwarz
IPC分类号： G06F15/00 , G06F7/50
CPC分类号： G06F7/4912
摘要： A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.
摘要翻译：一种在十进制算术逻辑单元结构中产生一个周期内的两个十进制操作数的数学运算的幅度结果的方法，其中十进制操作数是十六进制符号幅度格式。

8. 发明授权

US08522182B2 Generation of an end point report for a timing simulation of an integrated circuit 失效
标题翻译：生成集成电路定时仿真的终点报告
公开(公告)号：US08522182B2
公开(公告)日：2013-08-27
申请号：US13314514
申请日：2011-12-08
申请人： Ulrich Krauch , Kurt Lind , Alexander Woerner
发明人： Ulrich Krauch , Kurt Lind , Alexander Woerner
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.
摘要翻译：存储处理器的指令的计算机可读存储器。执行指令会导致加载单元定时数据，描述上层。执行指令会导致加载单元定时路径，并将宏定时数据加载到存储器中。指令的执行进一步导致用宏定时数据替换单元定时报告的至少一部分，以及计算到达时间，松弛和压摆。执行指令还可以根据到达时间，松弛和回转以及生成单位定时路径的终点报告（包括路径统计信息）来计算路径统计信息。

9. 发明申请

US20120246606A1 GENERATION OF AN END POINT REPORT FOR A TIMING SIMULATION OF AN INTEGRATED CIRCUIT 失效
标题翻译：用于整合电路的时序仿真的端点报告的生成
公开(公告)号：US20120246606A1
公开(公告)日：2012-09-27
申请号：US13314514
申请日：2011-12-08
申请人： Ulrich KRAUCH , Kurt LIND , Alexander WOERNER
发明人： Ulrich KRAUCH , Kurt LIND , Alexander WOERNER
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.
摘要翻译：存储处理器的指令的计算机可读存储器。执行指令会导致加载单元定时数据，描述上层。执行指令会导致加载单元定时路径，并将宏定时数据加载到存储器中。指令的执行进一步导致用宏定时数据替换单元定时报告的至少一部分，以及计算到达时间，松弛和压摆。执行指令还可以根据到达时间，松弛和回转以及生成单位定时路径的终点报告（包括路径统计信息）来计算路径统计信息。

10. 发明申请

US20080071852A1 METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD 审中-公开
标题翻译：在二进制算术加法算术单元中执行两个运算符的执行的方法来执行这种方法
公开(公告)号：US20080071852A1
公开(公告)日：2008-03-20
申请号：US11855658
申请日：2007-09-14
申请人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
发明人： Wilhelm Haller , Guenter Mayer , Veit Gernhoefer , Ulrich Krauch , Simon Fabel
IPC分类号： G06F7/50
CPC分类号： G06F7/507
摘要： A method and apparatus is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.
摘要翻译：提供了一种方法和装置，用于通过将两个操作数细分成相等位数的组来执行二进制运算单元中的两个操作数的减法，通过适当的算术运算，生成两个特定的位组的中间结果对分别包括相同位位置的操作数。每个中间结果对的第一个中间结果是在“0”的进位假设下产生的，并且每个中间结果对的第二个中间结果在“1”的进位假设下生成。选择来自每组比特的每个特定中间结果对的正确的中间结果，并且通过适当地合并所选择的正确的中间结果来生成两个操作数的减法的结果。

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