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1. 发明申请

US20090083569A1 Generating a Local Clock Domain Using Dynamic Controls 失效
标题翻译：使用动态控件生成本地时钟域
公开(公告)号：US20090083569A1
公开(公告)日：2009-03-26
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
IPC分类号： G04F10/00 , H04L7/00 , G06F1/04
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译：一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟门控信号产生时钟域控制，使得操作在所选择的周期上开始生效; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。

2. 发明授权

US08001411B2 Generating a local clock domain using dynamic controls 失效
标题翻译：使用动态控件生成本地时钟域
公开(公告)号：US08001411B2
公开(公告)日：2011-08-16
申请号：US11859819
申请日：2007-09-24
申请人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
发明人： Sean Michael Carey , William Vincent Huott , Christian Jacobi , Guenter Mayer , Timothy Gerard McNamara , Chung-Lung Kevin Shum , Hans-Werner Tast , Michael Hemsley Wood
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/3275 , G11C7/22 , G11C7/222 , G11C11/413 , Y02D10/14
摘要： A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times itscommencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes.
摘要翻译：一种用于在操作中产生本地时钟域的方法包括以下步骤：在操作期间接收用于逻辑的较慢部分的时钟频率测量; 产生本地信号以指示操作的开始并用作时钟选通信号; 将时钟门控信号锁存到选定的周期; 基于时钟选通信号产生时钟域控制，使得操作在所选择的周期上重新启动; 并且在未锁定的锁存器中传播时钟门控信号多个周期，使得第二操作被限制为被启动直到操作完成。

3. 发明授权

US07987384B2 Method, system, and computer program product for handling errors in a cache without processor core recovery 有权
标题翻译：用于在没有处理器核心恢复的情况下处理高速缓存中的错误的方法，系统和计算机程序产品
公开(公告)号：US07987384B2
公开(公告)日：2011-07-26
申请号：US12029516
申请日：2008-02-12
申请人： Christian Jacobi , Matthias Pflanz , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai
发明人： Christian Jacobi , Matthias Pflanz , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai
IPC分类号： G06F11/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译：用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。执行流水线从较高级别的存储位置访问所请求的数据的副本。

4. 发明申请

US20090216949A1 METHOD AND SYSTEM FOR A MULTI-LEVEL VIRTUAL/REAL CACHE SYSTEM WITH SYNONYM RESOLUTION 有权
标题翻译：具有同步分辨率的多级虚拟/实时缓存系统的方法和系统
公开(公告)号：US20090216949A1
公开(公告)日：2009-08-27
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译：具有同义词解析的多级虚拟/真实缓存系统的方法和系统。一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。

5. 发明授权

US08041894B2 Method and system for a multi-level virtual/real cache system with synonym resolution 有权
标题翻译：具有同义词解析的多级虚拟/真实缓存系统的方法和系统
公开(公告)号：US08041894B2
公开(公告)日：2011-10-18
申请号：US12036357
申请日：2008-02-25
申请人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
发明人： Barry W. Krumm , Christian Jacobi , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai , Ching-Farn E. Wu
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0817
摘要： Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.
摘要翻译：具有同义词解析的多级虚拟/真实缓存系统的方法和系统。一个示例性实施例包括多级高速缓存层级，其包括与一个或多个处理器核心和一组L2高速缓存相关联的一组L1高速缓存，其中所述一组L1高速缓存是所述一组L2高速缓存的子集，其中所述集合在一个给定的L2高速缓存下面的L1高速缓存与一个或多个处理器核心相关联。

6. 发明申请

US20090204766A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY 有权
标题翻译：方法，系统和计算机程序产品，用于处理高速缓存中的错误，无需处理器核心恢复
公开(公告)号：US20090204766A1
公开(公告)日：2009-08-13
申请号：US12029516
申请日：2008-02-12
申请人： Christian Jacobi , Matthias Pflanz , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai
发明人： Christian Jacobi , Matthias Pflanz , Chung-Lung Kevin Shum , Hans-Werner Tast , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1064 , G06F12/0855 , G06F12/0897
摘要： A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location.
摘要翻译：用于处理高速缓冲存储器中没有处理器核心恢复的错误的方法包括从处理器接收对数据的取出请求，同时发送取出的数据以及将获取的数据的奇偶校验与校验符相匹配的处理器。将获取的数据从较高级别的高速缓存接收到处理器的低级缓存中。在确定所获取的数据失败的情况下，指示所取出的数据被破坏的错误检查失败，所述方法包括请求执行流水线中断处理和刷新其内容，以及启动清理序列，其包括将无效请求发送到低级别缓存导致低级缓存删除与损坏的数据相关联的行，并请求执行管道重新启动。执行流水线从较高级别的存储位置访问所请求的数据的副本。

7. 发明授权

US08015362B2 Method and system for handling cache coherency for self-modifying code 有权
标题翻译：用于处理缓存一致性的自修改代码的方法和系统
公开(公告)号：US08015362B2
公开(公告)日：2011-09-06
申请号：US12031923
申请日：2008-02-15
申请人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译：一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示线路用于PSC操作。该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

8. 发明申请

US20090210627A1 METHOD AND SYSTEM FOR HANDLING CACHE COHERENCY FOR SELF-MODIFYING CODE 有权
标题翻译：用于处理自我修改代码的高速缓存的方法和系统
公开(公告)号：US20090210627A1
公开(公告)日：2009-08-20
申请号：US12031923
申请日：2008-02-15
申请人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Gregory W. Alexander , Christian Jacobi , Barry W. Krumm , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译：一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示线路用于PSC操作。该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。

9. 发明授权

US07890700B2 Method, system, and computer program product for cross-invalidation handling in a multi-level private cache 失效
标题翻译：用于多级私有缓存中的交叉无效处理的方法，系统和计算机程序产品
公开(公告)号：US07890700B2
公开(公告)日：2011-02-15
申请号：US12051736
申请日：2008-03-19
申请人： Ka Shan Choy , Jennifer A. Navarro , Chung-Lung Kevin Shum , Aaron Tsai
发明人： Ka Shan Choy , Jennifer A. Navarro , Chung-Lung Kevin Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor.
摘要翻译：提供了一种用于在多级私有缓存中进行交叉无效处理的方法，系统和计算机程序产品。该系统包括一个处理器。处理器包括与1级数据高速缓存，1级指令高速缓存，2级高速缓存和更高级高速缓存通信的取指地址寄存器逻辑。该处理器还包括一组在获取地址寄存器中实现的交叉无效快照计数器。每个交叉无效快照计数器跟踪在从较高级别的缓存返回相应的高速缓存未命中的新数据之前接收到的未决更高级别的交叉无效的量。该处理器还包括在取出地址寄存器上执行的逻辑，用于处理1级数据高速缓存未命中并与2级缓存进行接口。响应于新数据，并且在确定旧的交叉无效正在等待时，防止新数据被处理器使用。

10. 发明申请

US20100241899A1 Debugging for multiple errors in a microprocessor environment 有权
标题翻译：在微处理器环境中调试多个错误
公开(公告)号：US20100241899A1
公开(公告)日：2010-09-23
申请号：US12405418
申请日：2009-03-17
申请人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
发明人： Ulrich Mayer , Timothy John Slegel , Chung-Lung Kevin Shum , Frank Lehnert , Guenter Gerwig
IPC分类号： G06F11/20 , G06F9/30
CPC分类号： G06F11/1407 , G06F9/3863 , G06F9/3865 , G06F11/0721 , G06F11/076 , G06F11/0772
摘要： A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging.
摘要翻译：已经教导了一种新的方法和装置，用于存储由初始和随后的错误发生产生的用于调试的错误信息。在本发明中，使用具有多个位范围的寄存器来存储错误信息。第一个比特范围被分配给初始的错误信息。如果错误总数超过寄存器的容量，则最后一个错误将保留在最后一个位范围内。这样，宝贵的初始错误信息（以及最后一个错误信息）将可用于调试。

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