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1. 发明授权

US5412803A Communications system having plurality of originator and corresponding recipient buffers with each buffer having three different logical areas for transmitting messages in single transfer 失效
标题翻译：具有多个发起者和对应的接收缓冲器的通信系统，每个缓冲器具有三个不同的逻辑区域，用于在单次传送中发送消息
公开(公告)号：US5412803A
公开(公告)日：1995-05-02
申请号：US839652
申请日：1992-02-20
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/00 , G06F13/12 , G06F13/38 , H04L29/06 , H04L29/08 , H04L29/14
CPC分类号： G06F13/122 , H04L69/40 , H04L69/14
摘要： Buffers are provided in two elements between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to. Since the commands must be executed in the sequence in which they are received, a response to the cancel complete command ensures that there are no other cancel operation commands remaining in the receiver, allowing subsequent operations to start without danger of being canceled.
摘要翻译：缓冲器被提供在要传送数据的两个元件中，其中两个缓冲器仅由数据传送的发起者管理。传输消息只需要一次传输，第二次传输确认功能的完成，因为在实现的协议下向接收者传递消息。当发送请求时，在发送方开始一个消息定时器。当接收到请求的正常响应时，定时器被复位; 然而，如果消息操作的持续时间超过超时值，则启动消息超时过程。当取消命令发出时，设置第二个定时器。如果超过此定时器，则可以发出后续取消命令。如果发出后续取消命令，则必须发送取消完成命令并进行响应。由于命令必须按照接收的顺序执行，所以对取消完成命令的响应确保在接收器中不存在其他取消操作命令，允许后续操作开始而不会被取消危险。

2. 发明申请

US20050081080A1 Error recovery for data processing systems transferring message packets through communications adapters 审中-公开
标题翻译：数据处理系统通过通信适配器传输消息包的错误恢复
公开(公告)号：US20050081080A1
公开(公告)日：2005-04-14
申请号：US10685119
申请日：2003-10-14
申请人： Carl Bender , John Houston , Gregory Salyer
发明人： Carl Bender , John Houston , Gregory Salyer
IPC分类号： G06F11/00
CPC分类号： H04L41/0668
摘要： A method and system are provided for error recovery in the process of message packet transfer using communications adapters connected between data processing nodes and a switched network. The communications adapter are provided with internal storage that is capable of storing specific information concerning the failure of one or more message packet transfers. This storage may be queried from nodes external to the adapter to more precisely determine the error and to take corrective actions, where possible.
摘要翻译：提供了一种使用连接在数据处理节点和交换网络之间的通信适配器的消息分组传输过程中的错误恢复的方法和系统。通信适配器设置有能够存储关于一个或多个消息分组传送的故障的特定信息的内部存储器。可以从适配器外部的节点查询该存储，以更精确地确定错误并在可能的情况下采取纠正措施。

3. 发明授权

US5267240A Frame-group transmission and reception for parallel/serial buses 失效
标题翻译：并行/串行总线的帧组发送和接收
公开(公告)号：US5267240A
公开(公告)日：1993-11-30
申请号：US839986
申请日：1992-02-20
申请人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott , Vincent P. Zeyak, Jr.
发明人： Neil G. Bartow , Paul J. Brown , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott , Vincent P. Zeyak, Jr.
IPC分类号： H04L29/00 , H04J3/06 , H04L25/02 , H04L29/06 , H04L29/14 , G06K5/04
CPC分类号： H04J3/0629 , H04L69/14 , H04L69/40 , Y02B60/33
摘要： A system and method for asynchronously transmitting data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. In one embodiment, the transceivers for each member of the parallel bus asynchronously achieve synchronism at each end of the fiber. Thus the need for a common clock is eliminated. The receivers on each side of the bus determine the relative skew for each conductor by performing skew measurements on a calibration message generated by the transmitters on the other side of the bus. When the skew on all conductors, viewed from both sides of the bus, has been determined, the skew values are exchanged across the bus, thus enabling the transmitters to set proper frame spacing.

4. 发明授权

US5265232A Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data 失效
标题翻译：在所选处理器高速缓存中通过数据无效的一致性控制，而无需广播到不具有数据的处理器缓存
公开(公告)号：US5265232A
公开(公告)日：1993-11-23
申请号：US679900
申请日：1991-04-03
申请人： Patrick M. Gannon , Michael Ignatowski , Matthew A. Krygowski , Lishing Liu , Donald W. Price , William K. Rodiger , Gregory Salyer , Yee-Ming Ting , Michael P. Witt
发明人： Patrick M. Gannon , Michael Ignatowski , Matthew A. Krygowski , Lishing Liu , Donald W. Price , William K. Rodiger , Gregory Salyer , Yee-Ming Ting , Michael P. Witt
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/082 , G06F12/0811
摘要： A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).

5. 发明授权

US5680575A Interconnect failure detection and cache reset apparatus 失效
标题翻译：互连故障检测和缓存复位装置
公开(公告)号：US5680575A
公开(公告)日：1997-10-21
申请号：US443293
申请日：1995-05-17
申请人： Neil George Bartow , Robert Stanley Capowski , Louis Thomas Fasano , Thomas Anthony Gregg , Gregory Salyer , Douglas Wayne Westcott
发明人： Neil George Bartow , Robert Stanley Capowski , Louis Thomas Fasano , Thomas Anthony Gregg , Gregory Salyer , Douglas Wayne Westcott
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , G06F13/14
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for resetting a cache in a first device connected by a multilinelink to a memory in a second device. A transceiver in the first element connects to one end of each of the link lines and a transceiver in the second device connects to the other end. The transmitter in the first device transceiver is disabled in response to a failure of the transceiver to receive messages from the second device. The transmitter in the first device transceiver also selectively sends a reset sequence to the receiver in the second device. A detector detects when all of the receivers in the second device have either received a reset sequence or have detected that a transmitter in the first device is disabled. The detector sets a latch in response, representing that data in the second device cache is invalid. Optionally, the second device has responders which send responses over the link lines indicating receipt of a reset sequence. The transmitters in the first device switch to a disabled state when the responses are not received within a specified period.
摘要翻译：一种用于将通过多连接器连接的第一设备中的高速缓存重置到第二设备中的存储器的系统。第一元件中的收发器连接到每个链路线的一端，并且第二设备中的收发器连接到另一端。第一设备收发器中的发射机响应于收发器从第二设备接收消息的故障被禁用。第一设备收发器中的发射机还选择性地向第二设备中的接收机发送复位序列。检测器检测到第二设备中的所有接收器何时已经接收到重置序列或检测到第一设备中的发射机被禁用。检测器设置响应的锁存器，表示第二设备高速缓存中的数据无效。可选地，第二设备具有通过链路线发送响应的响应器，指示接收到重置序列。当在指定时间内没有收到响应时，第一个设备中的发射机切换到禁用状态。

6. 发明授权

US5548623A Null words for pacing serial links to driver and receiver speeds 失效
标题翻译：用于将串行链路用于起动和接收速度的空字
公开(公告)号：US5548623A
公开(公告)日：1996-08-20
申请号：US71150
申请日：1993-06-01
申请人： Daniel F. Casper , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Daniel F. Casper , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , H04L7/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom. Pacing information is exchanged on the link causing null words to be inserted at an optimum rate to compensate for slow receivers.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被视为配置，则在配置收发器表中进行条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目标 - 操作链路，以确保两个通道同意该组导体将形成操作链接。如果“预想 - 运营 - 链路”验证，则建立运营链路。在链路上交换起搏信息，导致以最佳速率插入空字来补偿慢速接收机。

7. 发明授权

US5418939A Concurrent maintenance of degraded parallel/serial buses 失效
标题翻译：并行维护降级并行/串行总线
公开(公告)号：US5418939A
公开(公告)日：1995-05-23
申请号：US070587
申请日：1993-06-01
申请人： Kenneth J. Fredericks , Thomas A. Gregg , Paul W. Jones , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott
发明人： Kenneth J. Fredericks , Thomas A. Gregg , Paul W. Jones , Gregory Salyer , Patrick J. Sugrue , Douglas W. Westcott
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , G06F11/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operation-Link verifies, the operational link is established therefrom.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被视为配置，则在配置收发器表中进行条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目标 - 操作链路，以确保两个通道同意该组导体将形成操作链接。如果Intended-Operation-Link验证，则建立操作链路。

8. 发明授权

US5357608A Configurable, recoverable parallel bus 失效
标题翻译：可配置的可并行总线
公开(公告)号：US5357608A
公开(公告)日：1994-10-18
申请号：US839657
申请日：1992-02-20
申请人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/00 , G06F15/17 , H04L29/04 , H04L29/06 , H04L29/08 , H04L29/14
CPC分类号： G06F15/17 , H04L29/06 , H04L69/40 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors will form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被认为是配置的，并且在Configured-Transceiver表中进行了一个条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目标 - 操作链路，以确保两个通道同意该组导体将形成操作链接。如果“预想 - 运营 - 链路”验证，则建立运营链路。

9. 发明授权

US4635186A Detection and correction of multi-chip synchronization errors 失效
标题翻译：检测和校正多芯片同步误差
公开(公告)号：US4635186A
公开(公告)日：1987-01-06
申请号：US506488
申请日：1983-06-20
申请人： Price W. Oman , Mark A. Rinaldi , Vito W. Russo , Gregory Salyer
发明人： Price W. Oman , Mark A. Rinaldi , Vito W. Russo , Gregory Salyer
IPC分类号： G06F9/38 , G06F9/22 , G06F9/28 , G06F13/42 , G06F11/00 , G06F13/00
CPC分类号： G06F13/4217 , G06F9/223 , G06F9/28
摘要： A uniprocessor if formed on plural independently controlled chips each including a primary instruction driven controller and a secondary error driven self-sequencing controller. Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line. Hardware monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch driving a common external ERROR line, an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.
摘要翻译：单个处理器如果形成在多个独立控制的芯片上，每个独立控制芯片包括主指令驱动控制器和辅助错误驱动自排序控制器。每个指令并行提供给每个主控制器，它在完成执行时产生一个EXIT信号到一个共同的外部EXIT行。硬件监视本地EXIT信号和公共EXIT线路状态，并且当检测到不匹配时激活辅助控制器，以设置驱动公共外部ERROR线的片上复位主要错误锁存器，其中还设置锁存并激活任何无效的辅助控制器以将其芯片驱动到第一预定状态并重置其锁存器。当不存在ERROR信号时，二级控制器通过ERROR程序同步循环，退出指令控制。

10. 发明授权

US5509122A Configurable, recoverable parallel bus 失效
标题翻译：可配置的可并行总线
公开(公告)号：US5509122A
公开(公告)日：1996-04-16
申请号：US71146
申请日：1993-06-01
申请人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
发明人： Neil G. Bartow , Robert S. Capowski , Louis T. Fasano , Thomas A. Gregg , Gregory Salyer , Douglas W. Westcott
IPC分类号： G06F13/12 , G06F15/17 , G06F15/173 , H04J3/06 , H04L7/10 , H04L29/06 , H04L29/08 , H04L29/14 , G06F11/00
CPC分类号： G06F13/122 , G06F15/17 , G06F15/17343 , H04J3/0629 , H04L29/06 , H04L69/40 , H04L7/10 , H04L69/14 , H04L69/323 , H04L69/324
摘要： A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link. The Intended-Operational-Link is verified to ensure that both channels agree on the set of conductors which form the operational link. If the Intended-Operational-Link verifies, the operational link is established therefrom.
摘要翻译：一种用于在数据处理复合体的元件之间传输信息的系统和用于建立这样的系统的方法。数据处理系统的两个元件通过物理链路连接，该物理链路包括在每个数据处理元件中的通道处附接到收发器的多个导体。一旦收发器已经同步，则交换命令和响应，这确保通道中的所有收发器连接到导体另一端上的相同通道。如果收发器被视为配置，则在配置收发器表中进行条目。搜索允许操作链表，其中包含允许成为操作链接的收发器集合。因此找到的收发器集合与Configured-Transceiver-Table进行比较，以验证集合中的所有成员是否已配置。如果找到一个匹配，这组收发器就成为一个Intended-Operational-Link。验证了目的 - 操作链路，以确保两个通道对形成操作链路的一组导体达成一致。如果“预想 - 运营 - 链路”验证，则建立运营链路。

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