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1. 发明授权

US06496166B1 Display apparatus 失效
标题翻译：显示装置
公开(公告)号：US06496166B1
公开(公告)日：2002-12-17
申请号：US09608150
申请日：2000-06-30
申请人： Makoto Onozawa , Yuji Sano , Michitaka Ohsawa , Takashi Sasaki , Noboru Akiyama , Fumitaka Asami , Kazuo Yoshiikawa , Hitoshi Hirakawa , Tomokatsu Kishi , Toyoshi Kawada
发明人： Makoto Onozawa , Yuji Sano , Michitaka Ohsawa , Takashi Sasaki , Noboru Akiyama , Fumitaka Asami , Kazuo Yoshiikawa , Hitoshi Hirakawa , Tomokatsu Kishi , Toyoshi Kawada
IPC分类号： G09G328
CPC分类号： G09G3/2965 , G09G3/2927 , G09G3/293 , G09G3/294 , G09G3/296
摘要： As is obvious from the description in the specification and the attached drawings, the present invention provides a display apparatus for displaying an image on a display panel by turning on pixels of said display panel, said display apparatus comprising: a display panel provided with: address electrodes driven by address pulses based on a video input signal; and sustain electrodes crossing said address electrodes and sandwiching electrical discharging units of pixels with said address electrodes and driven by sustain pulses; a sustain-electrode drive circuit for generating said sustain pulses and scan pulses, provided with a common circuit for generating said sustain pulses or said scan pulses in response to an operating state thereof and for supplying said scan pulses and said sustain pulses to said sustain electrodes.
摘要翻译：从说明书和附图的说明可以看出，本发明提供一种显示装置，用于通过打开所述显示面板的像素在显示面板上显示图像，所述显示装置包括：显示面板，设置有：地址基于视频输入信号的寻址脉冲驱动的电极; 并维持与所述寻址电极交叉的电极，并用所述寻址电极夹持像素的放电单元并由维持脉冲驱动; 用于产生所述维持脉冲和扫描脉冲的维持电极驱动电路，设置有用于响应于其工作状态产生所述维持脉冲或所述扫描脉冲的公共电路，并用于将所述扫描脉冲和所述维持脉冲提供给所述维持电极。

2. 发明授权

US5103192A Phase-difference detecting circuit and method of reducing power consumption in a PLL system 失效
标题翻译：相位差检测电路和降低PLL系统功耗的方法
公开(公告)号：US5103192A
公开(公告)日：1992-04-07
申请号：US534618
申请日：1990-06-06
申请人： Shinichi Sekine , Fumitaka Asami , Yukinori Kamizono
发明人： Shinichi Sekine , Fumitaka Asami , Yukinori Kamizono
IPC分类号： H03L7/187 , H03D13/00 , H03L7/08 , H03L7/089 , H03L7/183
CPC分类号： H03L7/0891 , H03D13/004 , H03L7/0802 , H03L7/183
摘要： A phase comparison circuit includes phase comparison device for generating an output signal corresponding to the difference in phase between a first input signal and a second input signal. The phase comparison device has an active mode, and a standby mode in which power consumption is reduced. A phase-difference detecting device is connected to the phase comparison device for outputting a control signal when the phase difference between the first and second input signals is smaller than a predetermined value. The phase comparison device is switched from the standby mode to the active mode in response to the control signal.

3. 发明授权

US4999708A Synchronous separation circuit 失效
标题翻译：同步分离电路
公开(公告)号：US4999708A
公开(公告)日：1991-03-12
申请号：US299534
申请日：1989-01-23
申请人： Tetsuo Aoki , Fumitaka Asami
发明人： Tetsuo Aoki , Fumitaka Asami
IPC分类号： H04N5/10
CPC分类号： H04N5/10
摘要： A synchronous separation circuit used in a television video circuit for generating a horizontal synchronizing signal and a vertical synchronizing signal from a composite synchronizing signal has: a unit for generating a clock signal used as a reference signal and having a frequency higher than the frequency of the horizontal synchronizing signal; a unit for counting the clock signal from a front edge of a pulse contained in the composite synchronizing signal; a unit for obtaining a horizontal synchronous separation and for determining a counting term and outputting the horizontal synchronizing signal after the counting unit counts from the front edge of the horizontal synchronizing signal to a predetermined number; and a unit for obtaining a vertical synchronous separation and for latching the composite synchronizing signal based on an output of the counting unit, separate the vertical synchronizing signal from the composite synchronizing signal.

4. 发明授权

US4904948A Phase comparator circuit 失效
标题翻译：相位比较电路
公开(公告)号：US4904948A
公开(公告)日：1990-02-27
申请号：US167712
申请日：1988-03-14
申请人： Fumitaka Asami
发明人： Fumitaka Asami
IPC分类号： H03D13/00 , H03K5/26
CPC分类号： H03L7/0891 , H03K5/26
摘要： A phase comparator circuit for comparing a phase of a first input signal with a second input signal and outputting a first output signal and a second output signal in accordance with a result of the comparison, and comprising two flip-flop circuits and a latch circuit, whereby, when the first and second input signals are in-phase, both first and second output signals are output.

5. 发明授权

US4437072A Lock detecting circuit for phase-locked loop frequency synthesizer 失效
标题翻译：锁相环频率合成器的锁定检测电路
公开(公告)号：US4437072A
公开(公告)日：1984-03-13
申请号：US420633
申请日：1982-09-21
申请人： Fumitaka Asami
发明人： Fumitaka Asami
IPC分类号： H03L7/18 , H03K5/26 , H03L7/08 , H03L7/089 , H03L7/095 , H04B1/10
CPC分类号： H03K5/26 , H03L7/0891 , H03L7/095 , Y10S331/02
摘要： A phase-locked loop circuit comprising a reference oscillator (1), a reference frequency divider (2) for dividing the output signal of the reference oscillator, a programmable frequency divider (3), a phase comparator (4) for monitoring the difference in phase between the output signal of the two frequency dividers, a lock detector (11) for generating a first signal which is pulse-shaped or rectangular when the above-mentioned difference in phase is generated, and a digital signal maintaining circuit (100) for converting the first signal into a second directed current signal.
摘要翻译：一种锁相环电路，包括参考振荡器（1），用于分频基准振荡器的输出信号的参考分频器（2），可编程分频器（3），相位比较器（4）两个分频器的输出信号之间的相位，当产生上述相位差时产生脉冲形或矩形的第一信号的锁定检测器（11），以及用于产生第二信号的数字信号维持电路将第一信号转换成第二定向电流信号。

6. 发明授权

US07002535B2 Display apparatus 失效
公开(公告)号：US07002535B2
公开(公告)日：2006-02-21
申请号：US10866302
申请日：2004-06-14
申请人： Makoto Onozawa , Yuji Sano , Michitaka Ohsawa , Takashi Sasaki , Noboru Akiyama , Fumitaka Asami , Kazuo Yoshiikawa , Hitoshi Hirakawa , Tomokatsu Kishi , Toyoshi Kawada
发明人： Makoto Onozawa , Yuji Sano , Michitaka Ohsawa , Takashi Sasaki , Noboru Akiyama , Fumitaka Asami , Kazuo Yoshiikawa , Hitoshi Hirakawa , Tomokatsu Kishi , Toyoshi Kawada
IPC分类号： G09G3/28
CPC分类号： G09G3/2965 , G09G3/2927 , G09G3/293 , G09G3/294 , G09G3/296
摘要： A display apparatus includes a display panel including address electrodes and sustain electrodes crossing the address electrodes, with pixels being sandwiched between the address electrodes and the sustain electrodes. A sustain-electrode drive circuit selectively generates both sustain pulses and scan pulses and supplies them to the sustain electrodes. An address-electrode drive circuit generates address pulses based on a video signal and supplies the address pulses to the address electrodes. A control-signal generation circuit generates a control signal for controlling the sustain-electrode drive circuit to generate a selected one of the sustain pulses and the scan pulses and supplies the control signal to the sustain-electrode drive circuit. In order to display an image on the display panel, the sustain-electrode drive circuit both specifies addresses of pixels to be turned on and turns on the pixels at the specified addresses.

7. 发明授权

US06636187B2 Display and method of driving the display capable of reducing current and power consumption without deteriorating quality of displayed images 失效
标题翻译：驱动显示器的显示和方法能够降低电流和功耗，而不会降低显示图像的质量
公开(公告)号：US06636187B2
公开(公告)日：2003-10-21
申请号：US09181648
申请日：1998-10-29
申请人： Masaya Tajima , Junichi Okayasu , Kiyoshi Takata , Katsuhiro Ishida , Takashi Fujisaki , Yoshimasa Awata , Nobuyoshi Kondo , Shinsuke Tanaka , Naoki Matsui , Fumitaka Asami
发明人： Masaya Tajima , Junichi Okayasu , Kiyoshi Takata , Katsuhiro Ishida , Takashi Fujisaki , Yoshimasa Awata , Nobuyoshi Kondo , Shinsuke Tanaka , Naoki Matsui , Fumitaka Asami
IPC分类号： G09G320
CPC分类号： G09G3/20 , G09G3/2018 , G09G3/2932 , G09G2310/0213 , G09G2310/0227 , G09G2310/0267 , G09G2330/021
摘要： A display has a panel, and first and second electrodes. The first and second electrodes define a matrix of cells on the panel. The second electrodes, which correspond to lines of the cells, are scanned to select the cell lines one by one. The first electrodes are driven to set display data for a selected one of the cell lines. The display also has a sequence setting unit for setting sequences of scanning the second electrodes, and a sequence selection unit for selecting one of the sequences that minimizes the current and power consumption of a first-electrode driver without deteriorating the quality of the displayed images.
摘要翻译：显示器具有面板，以及第一和第二电极。第一和第二电极定义面板上的单元格矩阵。扫描对应于细胞线的第二电极逐一选择细胞系。第一电极被驱动以设置所选择的一个细胞系的显示数据。显示器还具有用于设置扫描第二电极的顺序的序列设置单元，以及用于选择使第一电极驱动器的电流和功耗最小化的序列之一的序列选择单元，而不会劣化显示图像的质量。

8. 发明授权

US5434526A Output circuit and semiconductor integrated circuit device 失效
标题翻译：输出电路和半导体集成电路器件
公开(公告)号：US5434526A
公开(公告)日：1995-07-18
申请号：US284291
申请日：1994-08-02
申请人： Syouichi Tanigashira , Fumitaka Asami
发明人： Syouichi Tanigashira , Fumitaka Asami
IPC分类号： H01L27/092 , H01L21/8238 , H03K17/687 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/094 , H03K17/16
CPC分类号： H03K19/0013 , H03K19/00315 , H03K19/00361 , H03K2217/0018
摘要： The present invention relates to an output circuit and a semiconductor integrated circuit. It is an object of the present invention to cut off a passage of a current through a forward parasitic diode of a transistor connected to a power supply line and a ground line at a time of suspension of output operation of the relevant circuit, and to raise an output high level to the utmost and lower an output low level to the utmost at time of normal output operation. A complementary MOS high impedance output circuit composed of a first field effect transistor and a second field effect transistor is structured so as to include provision of a third field effect transistor for controlling one of a state of a backgate of the first field effect transistor and a state of a backgate of the second field effect transistor and also to include provision of a fourth field effect transistor for controlling one of the state of the backgate of the first and second field effect transistor complementarily to the control of the state of the backgate of the third field effect transistor.
摘要翻译：本发明涉及输出电路和半导体集成电路。本发明的目的是在暂停相关电路的输出操作时切断与连接到电源线和接地线的晶体管的正向寄生二极管的电流通过，并且提高在正常输出操作时最大限度地输出高电平并将输出低电平降至最低。构成由第一场效应晶体管和第二场效应晶体管组成的互补MOS高阻抗输出电路，以便包括提供第三场效应晶体管，用于控制第一场效应晶体管的背栅的状态和第二场效应晶体管的背栅的状态，还包括提供第四场效应晶体管，用于与第一和第二场效应晶体管的背栅的状态的控制互补地控制第一和第二场效应晶体管的背栅的状态之一第三场效应晶体管。

9. 发明授权

US4973973A Code converter and encoder for converting a unipolar binary coded signal into a bipolar binary coded signal 失效
标题翻译：用于将单极二进制编码信号转换为双极二进制编码信号的代码转换器和编码器
公开(公告)号：US4973973A
公开(公告)日：1990-11-27
申请号：US330528
申请日：1989-03-30
申请人： Masato Abe , Fumitaka Asami
发明人： Masato Abe , Fumitaka Asami
IPC分类号： H03M7/00 , H03M5/18 , H04N9/65
CPC分类号： H03M5/18
摘要： A code converter includes an extraction device for extracting a reference level from a binary-coded input signal, which is offset at a predetermined voltage level and which varies arbitrarily with the same polarity as the voltage level. A twos-complement conversion device, connected to the extraction device, converts the reference level into a twos-complement value. A creation device, connected to the extraction device and the twos-complement conversion device adds an output signal of the twos-complement conversion device and the binary-coded input signal, thereby producing a bipolar binary-coded output signal to which a polarity bit is added.

10. 发明授权

US4698529A Output control circuit to prevent output of initial spike noise 失效
标题翻译：输出控制电路，防止初始尖峰噪声的输出
公开(公告)号：US4698529A
公开(公告)日：1987-10-06
申请号：US736029
申请日：1985-05-20
申请人： Fumitaka Asami
发明人： Fumitaka Asami
IPC分类号： H03K19/003 , H03K17/22 , H03K19/0944 , H03B1/04 , H03K5/00 , H03K5/13
CPC分类号： H03K17/223 , H03K17/22
摘要： Initial spike noise which occurs, when an IC is switched on, is suppressed by an output control circuit provided between the output terminal of an inner logic circuit and an output circuit of the IC. The output control circuit clamps the input terminal of the output control circuit until the supply voltage builds up to a steady state. The output control circuit comprises two stages each connected between the supply voltage and ground. The first stage has a series connection of a first FET and first resistor, the second stage has a series connection of a second FET, third FET and second resistor. The first FET is controlled by a reset signal and turns off the second FET until the reset signal is released. The second FET turns off the third FET which transmits the output signal of the inner circuit to the output circuit of the IC. When the reset signal is released, the third FET and hence the output circuit begins operation.
摘要翻译：通过设置在内部逻辑电路的输出端子和IC的输出电路之间的输出控制电路来抑制IC接通时发生的初始尖峰噪声。输出控制电路钳位输出控制电路的输入端，直到供电电压达到稳定状态。输出控制电路包括两个级，每级连接在电源电压和地之间。第一级具有第一FET和第一电阻器的串联连接，第二级具有第二FET，第三FET和第二电阻器的串联连接。第一个FET由复位信号控制，并关闭第二个FET直到复位信号被释放。第二FET关闭将内部电路的输出信号发送到IC的输出电路的第三FET。当复位信号被释放时，第三个FET和输出电路开始工作。

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