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1. 发明授权

US5434526A Output circuit and semiconductor integrated circuit device 失效
标题翻译：输出电路和半导体集成电路器件
公开(公告)号：US5434526A
公开(公告)日：1995-07-18
申请号：US284291
申请日：1994-08-02
申请人： Syouichi Tanigashira , Fumitaka Asami
发明人： Syouichi Tanigashira , Fumitaka Asami
IPC分类号： H01L27/092 , H01L21/8238 , H03K17/687 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/094 , H03K17/16
CPC分类号： H03K19/0013 , H03K19/00315 , H03K19/00361 , H03K2217/0018
摘要： The present invention relates to an output circuit and a semiconductor integrated circuit. It is an object of the present invention to cut off a passage of a current through a forward parasitic diode of a transistor connected to a power supply line and a ground line at a time of suspension of output operation of the relevant circuit, and to raise an output high level to the utmost and lower an output low level to the utmost at time of normal output operation. A complementary MOS high impedance output circuit composed of a first field effect transistor and a second field effect transistor is structured so as to include provision of a third field effect transistor for controlling one of a state of a backgate of the first field effect transistor and a state of a backgate of the second field effect transistor and also to include provision of a fourth field effect transistor for controlling one of the state of the backgate of the first and second field effect transistor complementarily to the control of the state of the backgate of the third field effect transistor.
摘要翻译：本发明涉及输出电路和半导体集成电路。本发明的目的是在暂停相关电路的输出操作时切断与连接到电源线和接地线的晶体管的正向寄生二极管的电流通过，并且提高在正常输出操作时最大限度地输出高电平并将输出低电平降至最低。构成由第一场效应晶体管和第二场效应晶体管组成的互补MOS高阻抗输出电路，以便包括提供第三场效应晶体管，用于控制第一场效应晶体管的背栅的状态和第二场效应晶体管的背栅的状态，还包括提供第四场效应晶体管，用于与第一和第二场效应晶体管的背栅的状态的控制互补地控制第一和第二场效应晶体管的背栅的状态之一第三场效应晶体管。

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