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1. 发明申请

US20140215112A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 有权
标题翻译：高性能互连物理层
公开(公告)号：US20140215112A1
公开(公告)日：2014-07-31
申请号：US13976960
申请日：2013-03-15
申请人： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Ashish Gupta
发明人： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Ashish Gupta
IPC分类号： G06F13/42
CPC分类号： G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
摘要： Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a predefined sequence on each of the lanes.
摘要翻译：链路的重新初始化可以在不终止链路的链路的情况下进行，链路包括，发射机和接收机将以多个通道耦合到每个通道，并且链路的重新初始化包括传输每个通道上的预定义序列。

2. 发明申请

US20140115207A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 有权
标题翻译：高性能互连物理层
公开(公告)号：US20140115207A1
公开(公告)日：2014-04-24
申请号：US13976937
申请日：2013-03-27
申请人： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Debendra Das Sharma , Jeffrey C. Swanson
发明人： Venkatraman Iyer , Darren S. Jue , Robert G. Blankenship , Fulvio Spagna , Debendra Das Sharma , Jeffrey C. Swanson
IPC分类号： G06F13/42
CPC分类号： G06F13/4291 , G06F1/24 , G06F1/3287 , G06F13/1678 , G06F13/42 , G06F13/4282 , G06N99/005
摘要： A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
摘要翻译：周期性控制窗口嵌入在要通过串行数据链路发送的链路层数据流中，其中控制窗口被配置为提供物理层信息，包括用于启动数据链路上的状态转换的信息。可以在数据链路的链路发送状态期间发送链路层数据，并且控制窗口可以中断发送猝发。在一个方面，信息包括指示改变链路上的活动车道数目的尝试的链路宽度转换数据。

3. 发明授权

US06255876B1 Simple glitchless phase selection method for multiplexing the phase interpolated clocks 有权
标题翻译：用于多路复用相位内插时钟的简单无毛刺相位选择方法
公开(公告)号：US06255876B1
公开(公告)日：2001-07-03
申请号：US09426234
申请日：1999-10-22
申请人： Shin Chung Chen , Fulvio Spagna
发明人： Shin Chung Chen , Fulvio Spagna
IPC分类号： H03K3284
CPC分类号： G11B20/1426 , H04L7/0083 , H04L7/0337
摘要： A phase selector circuit for the interpolation of phase signals including a state machine for outputting data in accordance with a clock signal and a logic circuit for receiving said output data from said state machine, the logic circuit causing a clock-to-data delay for data falling longer than a clock-to-data delay for data rising.
摘要翻译：一种用于内插相位信号的相位选择器电路，包括用于根据时钟信号输出数据的状态机和用于从所述状态机接收所述输出数据的逻辑电路，所述逻辑电路引起数据的时钟到数据延迟比数据上升的时钟到数据延迟下降。

4. 发明申请

US20170179962A1 PHASE FREQUENCY DETECTOR 审中-公开
公开(公告)号：US20170179962A1
公开(公告)日：2017-06-22
申请号：US15391585
申请日：2016-12-27
申请人： Wenyan Vivian Jia , Shenggao Li , Fulvio Spagna
发明人： Wenyan Vivian Jia , Shenggao Li , Fulvio Spagna
IPC分类号： H03L7/087 , G04F10/00
CPC分类号： H03L7/087 , G04F10/005 , H03D13/00
摘要： Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

5. 发明申请

US20080267633A1 SPLIT EQUALIZATION FUNCTION FOR OPTICAL AND ELECTRICAL MODULES 审中-公开
标题翻译：光学和电气模块的分割均衡功能
公开(公告)号：US20080267633A1
公开(公告)日：2008-10-30
申请号：US11740505
申请日：2007-04-26
申请人： Jan Peeters Weem , Tom Mader , Fulvio Spagna
发明人： Jan Peeters Weem , Tom Mader , Fulvio Spagna
IPC分类号： H04B10/00
CPC分类号： H04B10/40
摘要： Briefly, in accordance with one or more embodiments, optical transceiver module includes a first equalizer disposed internal to the optical transceiver module that is capable of equalizing an electrical signal provided to a host board in combination with a second equalizer disposed on the host board in a split equalization type arrangement.
摘要翻译：简而言之，根据一个或多个实施例，光收发器模块包括设置在光收发器模块内部的第一均衡器，其能够将提供给主板的电信号与设置在主板上的第二均衡器组合在一起分离均衡型布置。

6. 发明授权

US06275524B1 Apparatus and method for reducing the time required to acquire synchronization with an incoming data stream 有权
标题翻译：用于减少获取与输入数据流同步所需时间的装置和方法
公开(公告)号：US06275524B1
公开(公告)日：2001-08-14
申请号：US09239760
申请日：1999-01-29
申请人： Fulvio Spagna
发明人： Fulvio Spagna
IPC分类号： H03H730
CPC分类号： G11B20/1403 , G11B20/10009 , H03L7/0807 , H03L7/091 , H03L7/093
摘要： The inventive apparatus includes a first filter which receives an analog-based input signal and a feedback signal, performs equalization on the analog-based input signal and the feedback signal, and outputs an equalized signal based on the analog-based input signal and the feedback signal. The first filter may include an analog finite impulse response filter. The apparatus also includes an analog to digital converter which receives the equalized signal and outputs a digital signal converted from the equalized signal in accordance with the feedback signal. In addition, the apparatus includes a phase detector which receives the digital signal, detects a phase difference therefrom and outputs a signal corresponding to a magnitude of the phase difference. The apparatus also includes a second filter and a voltage controlled oscillator. The second filter receives and filters the signal corresponding to a magnitude of the phase difference and outputs a filtered signal corresponding to a magnitude of the phase difference. The voltage controlled oscillator receives the filtered signal corresponding to a magnitude of the phase difference and outputs the feedback signal. The first filter performs equalization on the analog-based input signal and feedback signal in accordance with a function defined by an expression having a plurality of coefficients including a first coefficient. Significantly, only the first coefficient of the plurality of coefficients is set equal to a value of one and any remaining coefficients of the plurality of coefficients are set to a value of zero.
摘要翻译：本发明的装置包括接收基于模拟的输入信号和反馈信号的第一滤波器，对基于模拟的输入信号和反馈信号执行均衡，并且基于基于模拟的输入信号和反馈输出均衡的信号信号。第一滤波器可以包括模拟有限脉冲响应滤波器。该装置还包括模数转换器，其接收均衡信号并输出根据反馈信号从均衡信号转换的数字信号。此外，该装置包括相位检测器，其接收数字信号，检测其相位差，并输出与相位差大小对应的信号。该装置还包括第二滤波器和压控振荡器。第二滤波器接收和滤除与相位差的大小相对应的信号，并且输出与相位差的大小对应的滤波信号。压控振荡器接收对应于相位差大小的滤波信号并输出反馈信号。第一滤波器根据由包括第一系数的多个系数的表达式所定义的函数，对基于模拟的输入信号和反馈信号执行均衡。重要的是，仅将多个系数中的第一系数设置为等于1的值，并将多个系数中的任何剩余系数设置为零。

7. 发明申请

US20190305926A1 PROGRAMMBLE CLOCK DATA RECOVERY (CDR) SYSTEM INCLUDING MULTIPLE PHASE ERROR CONTROL PATHS 审中-公开
公开(公告)号：US20190305926A1
公开(公告)日：2019-10-03
申请号：US15939795
申请日：2018-03-29
申请人： Shenggao Li , Ji Chen , Michael De Vita , Fulvio Spagna , Guluke Tong
发明人： Shenggao Li , Ji Chen , Michael De Vita , Fulvio Spagna , Guluke Tong
IPC分类号： H04L7/033 , G06F13/40 , G06F13/42
摘要： Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase error information based on the input signal. A first circuit path provides proportional control information based on the data information and phase error information. A second circuit path provides integral control information based on the data information and phase error information. The first circuit path operates at a frequency higher than the second circuit path. The DCO generates a clock signal and controls the timing of the clock signal based on the integral control information and the proportional control information.

8. 发明授权

US08957705B2 Phase frequency detector 有权
标题翻译：相频检测器
公开(公告)号：US08957705B2
公开(公告)日：2015-02-17
申请号：US13617233
申请日：2012-09-14
申请人： Wenyan Jia , Shenggao Li , Fulvio Spagna
发明人： Wenyan Jia , Shenggao Li , Fulvio Spagna
IPC分类号： H03D13/00
CPC分类号： H03L7/087 , G04F10/005 , H03D13/00
摘要： Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
摘要翻译：描述了一种装置，包括：第一相位频率检测器（PFD），用于确定第一时钟信号和第二时钟信号之间的粗略相位差，第一PFD产生指示粗略相位差的第一输出; 以及耦合到所述第一PFD的第二PFD，以确定所述第一时钟信号和所述第二时钟信号之间的精细相位差，所述第二PFD产生指示所述精细相位差的第二输出。

9. 发明申请

US20140077841A1 PHASE FREQUENCY DETECTOR 有权
标题翻译：相位检测器
公开(公告)号：US20140077841A1
公开(公告)日：2014-03-20
申请号：US13617233
申请日：2012-09-14
申请人： Wenyan Jia , Shenggao Li , Fulvio Spagna
发明人： Wenyan Jia , Shenggao Li , Fulvio Spagna
IPC分类号： H03D13/00 , H03M1/50
CPC分类号： H03L7/087 , G04F10/005 , H03D13/00
摘要： Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.
摘要翻译：描述了一种装置，包括：第一相位频率检测器（PFD），用于确定第一时钟信号和第二时钟信号之间的粗略相位差，第一PFD产生指示粗略相位差的第一输出; 以及耦合到所述第一PFD的第二PFD，以确定所述第一时钟信号和所述第二时钟信号之间的精细相位差，所述第二PFD产生指示所述精细相位差的第二输出。

10. 发明授权

US06587529B1 Phase detector architecture for phase error estimating and zero phase restarting 有权
标题翻译：用于相位误差估计和零相重启的相位检测器架构
公开(公告)号：US06587529B1
公开(公告)日：2003-07-01
申请号：US09258827
申请日：1999-02-25
申请人： Robert B. Staszewski , Fulvio Spagna
发明人： Robert B. Staszewski , Fulvio Spagna
IPC分类号： H04L2500
CPC分类号： G11B20/10074 , G11B20/10 , G11B20/10009
摘要： A system and method for enabling an efficient Zero Phase Restart (ZPR) of a device. The structure is based on deploying normalized timing gradient (NTG) blocks (501 and 502) in pairs, each circuit employing an orthogonal phase error transfer function characteristic (having one TG circuit sample orthogonally in relation to the other), for example, PR4 and EPR4 modes ideal sampling instances of a preamble. An NTG block (501 or 502) is selected based on having a native timing sampling instance with a phase error that is closest to zero. Since there is an equal chance that either of the circuits in a circuit pair will be selected, if the circuit implementing the current non-native architecture is selected, a separate signal is generated. This signal adds the equivalent of 180° to the error value that is provided to the timing recovery circuit. For example, by iterating the process after the special case of a zero phase restart (ZPR) operation, the native sampling instance is “forced” to be selected thereafter.
摘要翻译：一种用于实现设备的高效零相位重启（ZPR）的系统和方法。该结构基于成对地部署归一化定时梯度（NTG）块（501和502），每个电路采用正交相位误差传递函数特性（具有相对于另一个的一个TG电路样本），例如PR4和 EPR4模式是前导码的理想采样实例。基于具有最接近零的相位误差的本地定时采样实例来选择NTG块（501或502）。由于选择电路对中的任何一个电路是平等的机会，如果选择了实现当前非本机架构的电路，则会产生单独的信号。该信号将相当于提供给定时恢复电路的误差值为180°。例如，通过在零阶段重启（ZPR）操作的特殊情况之后迭代该过程，此后本地采样实例被“强制”。

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