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1. 发明授权

US09229897B2 Embedded control channel for high speed serial interconnect 有权
标题翻译：用于高速串行互连的嵌入式控制通道
公开(公告)号：US09229897B2
公开(公告)日：2016-01-05
申请号：US13537837
申请日：2012-06-29
申请人： Venkatraman Iyer , Debendra Das Sharma , Robert G. Blankenship , Darren S. Jue
发明人： Venkatraman Iyer , Debendra Das Sharma , Robert G. Blankenship , Darren S. Jue
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4291
摘要： Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect are controlled via use of control channel data that is sent over one or more of the data lanes on a periodic basis. A link state cycle is employed that includes a link control period during which control information is transferred over the interconnect and a link control interval between link control periods during which other links states are implemented, such as for transferring data or operating the link in a low power state. The link state cycles at transmitter and receiver ports are synchronized to account for link transmit latencies, and the timing of link state cycles corresponding to a bidirectional exchange of link control information may be configured to support an overlapping implementation or to facilitate a request/response link control protocol.
摘要翻译：用于在具有多个数据通道的高速串行互连中嵌入控制信道的方法和装置。通过使用在周期性地通过一个或多个数据通道发送的控制信道数据来控制互连的操作方面。使用链路状态周期，其包括链路控制周期，在该链路控制周期期间控制信息通过互连传送，以及链路控制周期之间的链路控制间隔，在链路控制周期期间实现其他链路状态，例如用于传送数据或以低的速率操作链路电源状态在发射机和接收机端口处的链路状态周期被同步以考虑链路发射延迟，并且与链路控制信息的双向交换相对应的链路状态周期的定时可以被配置为支持重叠实现或促进请求/响应链路控制协议。

2. 发明授权

US08754972B2 Integrated multi-channel analog front end and digitizer for high speed imaging applications 有权
标题翻译：集成多通道模拟前端和数字化仪，用于高速成像应用
公开(公告)号：US08754972B2
公开(公告)日：2014-06-17
申请号：US13364308
申请日：2012-02-01
申请人： David L. Brown , Mansour Kermat , Lance Glasser , Henrik Nielsen , Guowu Zheng , Kurt Lehman , Kenneth F. Hatch , Alex Chuang , Venkatraman Iyer
发明人： David L. Brown , Mansour Kermat , Lance Glasser , Henrik Nielsen , Guowu Zheng , Kurt Lehman , Kenneth F. Hatch , Alex Chuang , Venkatraman Iyer
IPC分类号： H04N5/335 , H04N5/228
CPC分类号： H04N5/378 , H01L27/14634 , H04N5/3694 , H04N5/37206 , H04N5/37213
摘要： A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.
摘要翻译：用于高速图像处理的模块包括用于产生表示图像的多个模拟输出的图像传感器和用于同时处理多个模拟输出的多个HDD。每个HDD是被配置为并行处理预定的一组模拟输出的集成电路。 HDD的每个通道可以包括用于调节表示一个传感器模拟输出的信号的AFE，用于将经调节的信号转换成数字信号的ADC，以及用于校准和格式化数字信号以传送到芯片外的数据格式化块设备。 HDD和驱动电子设备与图像传感器组合成一个封装，以优化信号完整性和高动态范围，并通过使用同步的HDD通道实现高数据速率。组合多个模块可实现高度可扩展的成像子系统，以优化检测和计量应用。

3. 发明授权

US08717882B2 Repurposing data lane as clock lane by migrating to reduced speed link operation 有权
标题翻译：通过迁移到降低速度链路操作来重新定位数据通道作为时钟通道
公开(公告)号：US08717882B2
公开(公告)日：2014-05-06
申请号：US13175798
申请日：2011-07-01
申请人： Venkatraman Iyer , Robert G. Blankenship , Allen J. Baum
发明人： Venkatraman Iyer , Robert G. Blankenship , Allen J. Baum
IPC分类号： H04J3/06
CPC分类号： G06F11/1428 , G06F11/1423 , G06F11/1604
摘要： Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.
摘要翻译：描述通过迁移到降低速度链接操作将与数据通道重新设置为时钟通道有关的方法和装置。在一个实施例中，在检测到链路的时钟通道上的故障并且链路的多个数据通道中的一个被重新利用作为替换时钟通道时，链路的速度被降低。还公开并要求保护其他实施例。

4. 发明申请

US20140115374A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 有权
标题翻译：高性能互连物理层
公开(公告)号：US20140115374A1
公开(公告)日：2014-04-24
申请号：US13976927
申请日：2013-03-27
申请人： Venkatraman Iyer , Darren S. Jue , Jeff Willey , Robert G. Blankenship
发明人： Venkatraman Iyer , Darren S. Jue , Jeff Willey , Robert G. Blankenship
IPC分类号： G06F1/12
CPC分类号： G06F13/161 , G06F1/12 , G06F13/1673 , G06F13/4004 , G06F13/4068 , G06F13/4221 , H04L45/74 , H04L49/15
摘要： A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.
摘要翻译：同步计数器的复位与外部确定信号同步。进入链路发送状态进一步与确定信号同步。识别串行数据链路的目标延迟。接收与与数据链路相关联的同步计数器同步的数据序列。可以使用数据序列维持目标延迟。

5. 发明申请

US20070234735A1 FUEL-FLEXIBLE COMBUSTION SYTEM AND METHOD OF OPERATION 审中-公开
标题翻译：燃油灵活燃烧系统及其运行方法
公开(公告)号：US20070234735A1
公开(公告)日：2007-10-11
申请号：US11277655
申请日：2006-03-28
申请人： David Mosbacher , Joel Haynes , Jonathan Janssen , Justin Brumberg , Venkatraman Iyer
发明人： David Mosbacher , Joel Haynes , Jonathan Janssen , Justin Brumberg , Venkatraman Iyer
IPC分类号： F02C3/20
CPC分类号： F02C3/20 , Y02E20/16 , Y02E20/18
摘要： A combustor nozzle is provided. The combustor nozzle includes a first fuel system configured to introduce a hydrocarbon fuel into a combustion chamber to enable lean premixed combustion within the combustion chamber and a second fuel system configured to introduce a syngas fuel, a hydrocarbon fuel and diluents into the combustion chamber to enable diffusion combustion within the combustion chamber.
摘要翻译：提供了一种燃烧器喷嘴。燃烧器喷嘴包括第一燃料系统，其构造成将碳氢化合物燃料引入燃烧室以使得能够在燃烧室内进行稀薄预混合燃烧;以及第二燃料系统，其构造成将合成气燃料，烃类燃料和稀释剂引入燃烧室，以使能燃烧室内的扩散燃烧。

6. 发明授权

US5133062A RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory 失效
标题翻译： RAM缓冲器控制器，用于在随机存取存储器中提供模拟先进先出（FIFO）缓冲器
公开(公告)号：US5133062A
公开(公告)日：1992-07-21
申请号：US566743
申请日：1990-08-13
申请人： Sunil P. Joshi , Venkatraman Iyer
发明人： Sunil P. Joshi , Venkatraman Iyer
IPC分类号： G06F5/06
CPC分类号： G06F5/065 , G06F2205/064 , G06F2205/066
摘要： A RAM buffer is provided for managing the address inut lines of a RAM buffer to simulate the operation of two FIFO's therein. In addition, an apparatus is provided for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage transmit and receive FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Also disclosed is an apparatus for transmitting packets from said buffer organized into one or two linked lists. Further, an apparatus is provided for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, an apparatus and a method are provided for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information.
摘要翻译：提供RAM缓冲器，用于管理RAM缓冲器的地址线，以模拟其中的两个FIFO的操作。此外，提供了一种装置，用于允许使用RAM缓冲器控制器的局域网节点中的节点处理器进行随机访问，以管理发送和接收FIFO以对缓冲器的地址空间中的任何地址进行随机访问，而不限于FIFO 边界还公开了一种用于将分组从所述缓冲器发送到一个或两个链表的装置。此外，提供了一种装置，用于允许独立初始化RAM缓冲器控制器中当前未选择的任何指针，并允许由节点处理器进行读取或写入访问的软件请求。此外，提供了一种装置和方法，用于在分组结束时记录状态和长度信息，而不是在其前面，并且允许任何输入分组被刷新而不保存状态信息或在保存其状态信息的同时被刷新。

7. 发明授权

US4723243A CRC calculation machine with variable bit boundary 失效
标题翻译：具有可变位边界的CRC计算机
公开(公告)号：US4723243A
公开(公告)日：1988-02-02
申请号：US803466
申请日：1985-12-02
申请人： Sunil P. Joshi , Venkatraman Iyer
发明人： Sunil P. Joshi , Venkatraman Iyer
IPC分类号： G06F11/10 , H03M13/00 , H03M13/09 , G06F7/52
CPC分类号： H03M13/091
摘要： There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRS calculation. Several different architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be performed on all bytes of a message while excluding some selected number of bits in the first byte is also disclosed.
摘要翻译：这里公开了CRC计算电路，其可以在每个字节时钟周期的8位原始输入数据上计算CRC校验位。计算装置使用8行移位链接，每行的输入耦合到前一行的数据输出。每个移动链接将其输入位移位到最高有效位一位位置，并且所选择的移位链路在它们的输入位和输入异或门的输出之间执行异或运算，其异或运算的一个输入位与校验和寄存器最高有效字节中的位。字节宽输出总线用于通过在输出周期期间禁用移位链路阵列来访问来自校验和寄存器的最终校验位，使得CRC数据的字节可以通过阵列移位到位，每个字节每字节周期一个字节时钟。提供用于将所有逻辑1强制到第一行移位链路的数据输入的预设逻辑，使得可以在CRS计算的第一个时钟周期期间预设该机器。公开了几种不同的体系结构，用于允许单独计算头部分组上的CRC比特和数据分组，其中数据分组上的CRC比特可以仅针对数据计算，或者数据加上头部的头部和CRC比特。还公开了允许对消息的所有字节执行CRC计算的逻辑，同时排除第一字节中的某些所选位数。

8. 发明授权

US09104793B2 Method and system of adapting communication links to link conditions on a platform 有权
标题翻译：通信链路适应平台上的链接条件的方法和系统
公开(公告)号：US09104793B2
公开(公告)日：2015-08-11
申请号：US12890252
申请日：2010-09-24
申请人： Venkatraman Iyer , Arvind Kumar , Santanu Chaudhuri , Darren S. Jue , Dennis R. Halicki
发明人： Venkatraman Iyer , Arvind Kumar , Santanu Chaudhuri , Darren S. Jue , Dennis R. Halicki
IPC分类号： G06F13/40 , G06F13/36 , H04L12/40 , G06F13/42 , H04L12/00
CPC分类号： G06F13/36 , G06F13/4072 , G06F13/4291 , H04L12/00 , H04L12/40052 , H04L12/4013 , H04L12/40136
摘要： A method and system to adapt communication links statically and/or dynamically to their individual link conditions on a platform. The communicatively coupled devices have logic to adapt one or more settings of a respective one or more communication links with another device based at least in part on a respective metric of received data patterns from the respective one or more communication links. The communicatively coupled devices in the platform have a back channel to allow feedback or information to be sent from one receiving device to a transmitting device in one embodiment of the invention.
摘要翻译：一种方法和系统，用于使通信链路在平台上静态和/或动态地适应其各自的链路条件。所述通信耦合设备具有至少部分地基于来自相应的一个或多个通信链路的接收数据模式的相应度量而将相应的一个或多个通信链路的一个或多个通信链路的一个或多个设置适配到另一设备的逻辑。在本发明的一个实施例中，平台中的通信耦合设备具有反向信道以允许从一个接收设备向发送设备发送反馈或信息。

9. 发明申请

US20140281071A1 OPTICAL MEMORY EXTENSION ARCHITECTURE 审中-公开
标题翻译：光学存储器扩展架构
公开(公告)号：US20140281071A1
公开(公告)日：2014-09-18
申请号：US13844083
申请日：2013-03-15
申请人： JIANPING JANE XU , DONALD FAW , VENKATRAMAN IYER
发明人： JIANPING JANE XU , DONALD FAW , VENKATRAMAN IYER
IPC分类号： G06F13/42
CPC分类号： G06F13/42 , G06F13/4045
摘要： An optical memory extension architecture. A first electrical logic circuit on a first die communicates data according to a packetized, point-to-point interconnect protocol at a full data rate. A first gasket circuit is coupled to receive the data from the first electrical logic circuit. The first gasket circuit causes the data to be converted to an optical format to be transmitted at a rate that is at least double the full data rate. A second gasket circuit is coupled to receive the data in the optical format from the first gasket circuit. The second gasket circuit causes the data to be converted to an electrical format conforming to the packetized, point-to-point interconnect protocol. A second electrical logic circuit on a second die is coupled to receive the data from the first electrical logic circuit through the first gasket circuit and the second gasket circuit.
摘要翻译：光学存储器扩展架构。第一芯片上的第一电逻辑电路以全数据速率根据打包的点对点互连协议传送数据。第一垫片电路被耦合以从第一电逻辑电路接收数据。第一垫片电路使得数据被转换成以至少是全数据速率的两倍的速率传输的光学格式。第二垫片电路被耦合以从第一垫片电路接收光学格式的数据。第二垫片电路使得数据被转换成符合分组化的点对点互连协议的电格式。第二管芯上的第二电逻辑电路被耦合以通过第一衬垫电路和第二衬垫电路从第一电逻辑电路接收数据。

10. 发明授权

US08831666B2 Link power savings with state retention 有权
标题翻译：链接省电与状态保留
公开(公告)号：US08831666B2
公开(公告)日：2014-09-09
申请号：US12495706
申请日：2009-06-30
申请人： Naveen Cherukuri , Jeffrey Wilcox , Venkatraman Iyer , Selim Bilgin , David D. Dunning , Robin Tim Frodsham , Theodore Z. Schoenborn , Sanjay Dabral
发明人： Naveen Cherukuri , Jeffrey Wilcox , Venkatraman Iyer , Selim Bilgin , David D. Dunning , Robin Tim Frodsham , Theodore Z. Schoenborn , Sanjay Dabral
IPC分类号： H04B7/00
CPC分类号： G06F1/3287 , G06F1/3296 , H04W52/0219 , H04W52/0229 , Y02D70/122
摘要： Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.
摘要翻译：描述了与链路功率节省与状态保持有关的方法和设备。在一个实施例中，通过串行链路耦合的两个代理的一个或多个组件在空闲时段期间被关闭，同时保持每个代理中的链路状态。还公开了其他实施例。

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