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1. 发明专利

JP2009213372A Plant cultivation material, and method for producing dried bean curd refuse 审中-公开
标题翻译：植物培养材料及其制造方法
公开(公告)号：JP2009213372A
公开(公告)日：2009-09-24
申请号：JP2008058146
申请日：2008-03-07
申请人： Lak Ji Chen , ラクジーチュウ
发明人： CHEN LAK JI
IPC分类号： A01G1/00 , A01G9/02
CPC分类号： A01G9/1086 , A01G2031/002 , A01G2031/008
摘要： PROBLEM TO BE SOLVED: To provide plant cultivation material excellent in growing plants and applying slight load on the environment even though easily and inexpensively produced, having wide flexibility in design, easy to handle, and thereby utilized for various kinds of purposes. SOLUTION: The plant cultivation material 10 is obtained through: well admixing a plant-originated substance produced by pulverizing or crushing thinned wood, barks, pruned branches and/or the like of logged trees and the like into chips each in a prescribed size, fibers or powder, with dried bean curd refuse with a mixer or the like, or by hands followed by adding aqueous binder (emulsion adhesive) to the mixture; and well mixing the mixture with a mixer or by hands so as to turn into pasty one; flowing the pasty mixture into a prescribed-shaped mold 20 to be pressurized via hydraulic press or the like into a prescribed shape followed by taking the mixture out of the mold 20 to dry the mixture. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使容易且廉价地生产，提供在生长中的植物和施加轻微负荷的植物栽培材料，具有广泛的设计灵活性，易于处理，从而用于各种目的。解决方案：通过以下方式获得植物栽培材料10：通过将已登记的树木等的稀薄木材，树皮，树枝，树枝等的粉碎或破碎而制成的植物产生的物质均匀地混合成规定的碎片尺寸，纤维或粉末，用搅拌机等的干豆腐垃圾，或用手，然后向混合物中加入水性粘合剂（乳液粘合剂）; 并将混合物与搅拌机或手混合，以便变成糊状的; 将糊状混合物流入规定形状的模具20中，以通过液压机等将其加压成规定形状，然后将混合物从模具20中取出以干燥混合物。版权所有（C）2009，JPO＆INPIT

2. 发明申请

WO2021236859A1 SYNTHESIS OF FLUORINATED NUCLEOTIDES 审中-公开
公开(公告)号：WO2021236859A1
公开(公告)日：2021-11-25
申请号：PCT/US2021/033286
申请日：2021-05-20
申请人： MERCK SHARP & DOHME CORP. , ARMIGER, Travis , BELYK, Kevin, M. , BENKOVICS, Tamas , CHUNG, Cheol, K. , JI CHEN, Yining , JOHNSON, Heather Claire , KLAPARS, Artis , LIU, Zhijian , LIU, Zhuqing , MOORE, Jeffrey, C. , NEEL, Andrew, J. , PENG, Feng , RUMMELT, Stephan, M. , SALEHI MARZUARANI, Nastaran , SHERRY, Benjamin, D. , SONG, Zhiguo Jake , TURNBULL, Ben William Hulme , WANG, Lu , XU, Feng
发明人： ARMIGER, Travis , BELYK, Kevin, M. , BENKOVICS, Tamas , CHUNG, Cheol, K. , JI CHEN, Yining , JOHNSON, Heather Claire , KLAPARS, Artis , LIU, Zhijian , LIU, Zhuqing , MOORE, Jeffrey, C. , NEEL, Andrew, J. , PENG, Feng , RUMMELT, Stephan, M. , SALEHI MARZUARANI, Nastaran , SHERRY, Benjamin, D. , SONG, Zhiguo Jake , TURNBULL, Ben William Hulme , WANG, Lu , XU, Feng
IPC分类号： A61K31/708 , A61K31/7076 , A61K31/7064 , A61K31/706
摘要： The present invention relates to efficient processes useful in the preparation of fluorinated nucleosides, such as (2S,3R,4S,5R)-5-(2-amino-6-oxo-1,6-dihydro-9H-purin-9-yl)-3-fluoro-4-hydroxy-2-(mercaptomethyl)tetrahydrofuran-3-yl dihydrogen phosphate, also known as 3´-fluoro-thio-guanosine monophosphate or 3´-F-thio-GMP. Such fluorinated nucleosides may be useful as a biologically active compound and or as an intermediate for the synthesis of more complex biologically active compounds. The present invention also encompasses intermediates useful in the disclosed synthetic processes and the methods of their preparation. (I)

3. 发明申请

WO2004066532A8 IMPLEMENT METHOD AND APPARATUS FOR DOWNLINK SYNCHRONIZATION SUBSYSTEM 审中-公开
标题翻译：下行链路同步子系统的实现方法和装置
公开(公告)号：WO2004066532A8
公开(公告)日：2004-09-30
申请号：PCT/CN0300061
申请日：2003-01-23
申请人： LINKAIR COMM INC , FANG LI , JI CHEN , LIU JINGBO , ZHANG YONGSHENG
发明人： FANG LI , JI CHEN , LIU JINGBO , ZHANG YONGSHENG
IPC分类号： H04B1/707 , H04J13/00
CPC分类号： H04B1/70735 , H04B1/7077 , H04B1/7083 , H04B2201/70702
摘要： The present invention relates to an implement method and apparatus for downlink synchronization subsystem, which can detect the boundary of initial frame, and the initial frequency can be catched by using the result of initial frame boundary detection, Then, it can carry the cell search and selection, the multipath signal searching and tracing, the carrier frequency tracking, and timing frequency tracking, In CDMA system, by implementing the frequency catching, downlink synchronization acquisition and cell identification, providing multipath information of traffic channel, and running the carrier frequency tracking, the present invention can ensure the accuracy of timing frequency, and have the characteristic of simplicity and utility.
摘要翻译：本发明涉及一种下行链路同步子系统的实现方法和装置，它可以检测初始帧的边界，利用初始帧边界检测的结果可以捕获初始频率，然后进行小区搜索和在CDMA系统中，通过实现频率捕获，下行同步捕获和小区识别，提供业务信道的多径信息，并运行载波频率跟踪，本发明可以保证定时频率的准确性，具有简单实用的特点。

4. 发明授权

US10219834B2 Use of absorption material to reduce radio frequency-induced heating in external fixation devices 有权
公开(公告)号：US10219834B2
公开(公告)日：2019-03-05
申请号：US14879383
申请日：2015-10-09
申请人： Ji Chen
发明人： Ji Chen
IPC分类号： A61B17/60 , A61B5/055 , A61B17/62 , A61B17/64
摘要： The present invention in general provides methods for reducing RF-induced heating in an external fixation device including at least two bars, at least two clamps and at least two pins; and external fixation devices with significantly lower RF heating at the pins' tips when compared to other external fixation devices.

5. 发明授权

US09328413B2 Method for preparing graphene nanoribbon on insulating substrate 有权
标题翻译：在绝缘基板上制备石墨烯纳米棒的方法
公开(公告)号：US09328413B2
公开(公告)日：2016-05-03
申请号：US13580240
申请日：2011-08-05
申请人： Shujie Tang , Guqiao Ding , Xiaoming Xie , Ji Chen , Chen Wang , Mianheng Jiang
发明人： Shujie Tang , Guqiao Ding , Xiaoming Xie , Ji Chen , Chen Wang , Mianheng Jiang
IPC分类号： C23C16/26 , B05D3/00 , C23C16/02 , B82Y30/00 , B82Y40/00 , C01B31/04
CPC分类号： C23C16/0218 , B82Y30/00 , B82Y40/00 , C01B32/184 , C01B32/186 , C01B2204/06 , C23C16/0272 , C23C16/26 , Y10T428/2918
摘要： A method for growing a graphene nanoribbon on an insulating substrate having a cleavage plane with atomic level flatness is provided, and belongs to the field of low-dimensional materials and new materials. The method includes the following steps. Step 1: Cleave an insulating substrate to obtain a cleavage plane with atomic level flatness, and prepare a single atomic layer step. Step 2: Directly grow a graphene nanoribbon on the insulating substrate having regular single atomic steps. In the method, a characteristic that nucleation energy of graphene on the atomic step is different from that on the flat cleavage plane is used, and conditions, such as the temperature, intensity of pressure and supersaturation degree of activated carbon atoms, are adjusted, so that the graphene grows only along a step edge into a graphene nanoribbon of an adjustable size. The method is mainly applied to the field of new-type graphene optoelectronic devices.
摘要翻译：提供了在具有原子级平坦度的解理面的绝缘基板上生长石墨烯纳米棒的方法，属于低维材料和新材料领域。该方法包括以下步骤。步骤1：切割绝缘基板以获得具有原子级平面度的解理面，并制备单个原子层步骤。步骤2：在具有规则单原子台阶的绝缘基板上直接生长石墨烯纳米纤维。在该方法中，使用原子台阶上的石墨烯的成核能与平坦解理面不同的特征，调节活性碳原子的温度，压力强度和过饱和度等条件，因此石墨烯仅沿着台阶边缘生长成可调节尺寸的石墨烯纳米棒。该方法主要应用于新型石墨烯光电器件领域。

6. 发明授权

US09117677B2 Semiconductor integrated circuit having a resistor and method of forming the same 有权
标题翻译：具有电阻器的半导体集成电路及其形成方法
公开(公告)号：US09117677B2
公开(公告)日：2015-08-25
申请号：US13272389
申请日：2011-10-13
申请人： Wei Yu Ma , Kuo-Ji Chen , Fang-Tsun Chu , Ta-Pen Guo
发明人： Wei Yu Ma , Kuo-Ji Chen , Fang-Tsun Chu , Ta-Pen Guo
IPC分类号： H01L27/06 , H01L21/768 , H01L27/02 , H01L23/522
CPC分类号： H01L27/0266 , H01L21/76895 , H01L23/5228 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.
摘要翻译：本申请公开了一种半导体集成电路，包括其上形成有电气器件的衬底，形成在衬底上的局部互连层，以及形成在局部互连层上的全局互连层。局部互连层具有第一组导电结构，其布置成在各个电气设备之间，电气设备及其相邻的电气设备之一中，或垂直设备和全局互连层之间电连接。第一组导电结构中的至少一个被配置为具有大于50欧姆的电阻值。全局互连层具有布置成经由第一组导电结构电连接电器件的第二组导电结构。

7. 发明申请

US20140210014A1 METHOD AND APPARATUS FOR FORMING AN INTEGRATED CIRCUIT WITH A METALIZED RESISTOR IN A STANDARD CELL CONFIGURATION 有权
标题翻译：在标准电池配置中用金属化电阻形成集成电路的方法和装置
公开(公告)号：US20140210014A1
公开(公告)日：2014-07-31
申请号：US13779783
申请日：2013-02-28
申请人： Wei Yu MA , Bo-Ting CHEN , Ting Yu CHEN , Kuo-Ji CHEN , Li-Chun TIEN
发明人： Wei Yu MA , Bo-Ting CHEN , Ting Yu CHEN , Kuo-Ji CHEN , Li-Chun TIEN
IPC分类号： H01L27/02
CPC分类号： H01L27/0288 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/0248 , H01L27/0629 , H01L27/11807 , H01L28/20 , H01L28/24
摘要： An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.
摘要翻译：集成电路包括半导体器件层，其包括在栅电极线之间具有固定栅电极间距的标准单元配置和在标准单元配置的固定栅电极间距之间由金属形成的电阻。在一个实施例中，集成电路可以是具有由金属形成的电阻器的交叉域标准单元的充电器件模型（CDM）静电放电（ESD）保护电路。制造集成电路的方法包括：形成由栅电极间距分开的多个栅极电极线，以形成芯标准电池器件，在栅电极间距内施加至少第一金属层以形成电阻器的一部分，以及施加至少第二金属层以耦合到第一金属层以形成电阻器的另一部分。

8. 发明授权

US08743515B2 ESD clamp with novel RC triggered circuit 有权
标题翻译：具有新型RC触发电路的ESD钳位
公开(公告)号：US08743515B2
公开(公告)日：2014-06-03
申请号：US13349962
申请日：2012-01-13
申请人： Tzu-Yi Yang , Kuo-Ji Chen
发明人： Tzu-Yi Yang , Kuo-Ji Chen
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： Some embodiments relate to an area efficient electrostatic discharge (ESD) clamp comprising an RC trigger circuit, having one or more low-voltage, thin-oxide devices, which is configured to operate with a high-voltage power supply. In some embodiments, the ESD clamp comprises an RC trigger circuit connected between a first circuit node having a first voltage and a second circuit node having a second voltage. The RC trigger circuit comprises a resistive element connected in series with a thin-oxide MOS capacitor. The MOS capacitor has a source and drain connected to an intermediate supply voltage between the first and second voltage, and a body connected to the second voltage. By connecting the source and drain to the intermediate supply voltage, the thin-oxide MOS capacitor is able to reliably operate with a high-voltage power supply.
摘要翻译：一些实施例涉及包括具有一个或多个低压，薄氧化物装置的RC触发电路的区域有效的静电放电（ESD）钳位，其被配置为利用高压电源进行操作。在一些实施例中，ESD钳位包括连接在具有第一电压的第一电路节点和具有第二电压的第二电路节点之间的RC触发电路。 RC触发电路包括与薄氧化物MOS电容器串联连接的电阻元件。 MOS电容器具有连接到第一和第二电压之间的中间电源电压的源极和漏极以及连接到第二电压的主体。通过将源极和漏极连接到中间电源电压，薄氧化物MOS电容器能够使用高压电源可靠地工作。

9. 发明授权

US08730013B2 RFID-based book tagging device and method 有权
标题翻译：基于RFID的书签标签设备及方法
公开(公告)号：US08730013B2
公开(公告)日：2014-05-20
申请号：US13242718
申请日：2011-09-23
申请人： Horng-Ji Chen
发明人： Horng-Ji Chen
IPC分类号： G06K7/01
CPC分类号： G06Q10/087 , G06K19/0722
摘要： The present invention relates to a radio frequency identification (RFID) device and method for book tagging, using which a RFID tag which is designed to attach to a book is first being scanned and detected in view of optimizing the RFID tag's signal strength and its effective reading rate as well so as to determine a position on the book for the RFID tag to attach thereat while allowing the detection to the RFID tag to be prevented from being adversely affected by metals or magnetic materials that are situated ambient to the book.
摘要翻译：本发明涉及一种用于书签的射频识别（RFID）装置和方法，使用该RFID标签设计成附着到书籍上的RFID标签首先被扫描和检测，从而优化RFID标签的信号强度及其有效性读取速度，以便确定RFID标签附着在书上的位置，同时允许RFID标签的检测被不利地受到位于书本周围的金属或磁性材料的不利影响。

10. 发明申请

US20140029142A1 FAILSAFE ESD PROTECTION 有权
标题翻译： FAILSAFE ESD保护
公开(公告)号：US20140029142A1
公开(公告)日：2014-01-30
申请号：US13557520
申请日：2012-07-25
申请人： Wei Yu Ma , Kou-Ji Chen
发明人： Wei Yu Ma , Kou-Ji Chen
IPC分类号： H02H9/04
CPC分类号： H02H9/04 , H02H9/046
摘要： Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.
摘要翻译：提供了一种或多种用于提供故障安全静电放电（ESD）保护的技术和/或系统。在一个实施例中，通过将电压故障安全（VFS）电源电压连接到NWELL电路接口（例如PMOS晶体管）并将PAD连接到VFS或NWELL电路接口中的至少一个来提供ESD保护。为此，要保护免受ESD（例如，可操作地连接到PAD的电路）的电路具有故障安全ESD保护（例如，使得可以使用非快速恢复的NMOS器件来放电ESD电流，其中非快速恢复NMOS 通常消耗更少的半导体不动产，并且与快速恢复NMOS相比，生产的复杂度较低）。以这种方式，有效地提供故障安全ESD保护。

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