专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09494987B2 Processing system with low power wake-up pad 有权
标题翻译：具有低功率唤醒垫的处理系统
公开(公告)号：US09494987B2
公开(公告)日：2016-11-15
申请号：US14093473
申请日：2013-11-30
申请人： Dzung T. Tran , Rishi Bhooshan , Rakesh Pandey , Fujio Takeda
发明人： Dzung T. Tran , Rishi Bhooshan , Rakesh Pandey , Fujio Takeda
IPC分类号： G06F1/26 , H01L27/02 , H01L29/06 , G06F1/32 , H01L29/786
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/3287 , H01L27/0222 , H01L29/0611 , H01L29/78609 , Y02D10/171
摘要： An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.
摘要翻译：集成电路包括输入/输出焊盘，输入电路和输出电路。输入电路耦合到输入/输出焊盘，该输入/输出焊盘接收包括唤醒信号的输入信号，该唤醒信号指示集成电路何时从掉电模式切换到活动模式。输出电路耦合到输入/输出焊盘，该输入/输出焊盘向输入/输出焊盘提供输出信号。输出电路包括在阱中的第一P沟道晶体管，其具有耦合到输入/输出焊盘的漏极以及耦合到电源端子的源极。电源端子在活动模式期间接收第一电源电压，并且在掉电模式期间与任何电源解耦。响应于唤醒信号，阱被耦合到唤醒信号，该唤醒信号指示从掉电模式到活动模式的改变。

2. 发明申请

US20070147139A1 Controller for controlling a source current to a memory cell, processing system and methods for use therewith 有权
标题翻译：用于控制到存储器单元的源电流的控制器，用于其的处理系统和方法
公开(公告)号：US20070147139A1
公开(公告)日：2007-06-28
申请号：US11249963
申请日：2005-10-13
申请人： Fujio Takeda
发明人： Fujio Takeda
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a read current state when a column containing the memory cell is selected.
摘要翻译：用于控制用于静态随机存取存储器（SRAM）的存储单元的源电流的控制器包括用于向存储单元提供偏置电流的偏置发生器。当选择包含存储单元的列时，读取电流发生器将存储器单元的源电流控制到读取当前状态。

3. 发明申请

US20070109890A1 Memory, processing system and methods for use therewith 有权
标题翻译：记忆，处理系统及其使用方法
公开(公告)号：US20070109890A1
公开(公告)日：2007-05-17
申请号：US11652327
申请日：2007-01-11
申请人： Fujio Takeda
发明人： Fujio Takeda
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/12 , G11C2207/005
摘要： A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected bitline as a sense amplifier input in response to the boosted column enable signal. A sense amplifier produces a data output.
摘要翻译：存储器包括耦合到存储器单元阵列的选定位线。列升压器产生升压列使能信号。列复用器响应于升压列使能信号，将所选位线上的信号作为读出放大器输入传递。读出放大器产生数据输出。

4. 发明申请

US20070091700A1 MEMORY, PROCESSING SYSTEM AND METHODS FOR USE THEREWITH 有权
标题翻译：存储器，处理系统及其使用方法
公开(公告)号：US20070091700A1
公开(公告)日：2007-04-26
申请号：US11257816
申请日：2005-10-25
申请人： Fujio Takeda
发明人： Fujio Takeda
IPC分类号： G11C7/02
CPC分类号： G11C7/1051 , G11C7/1012 , G11C7/12 , G11C2207/005
摘要： A memory includes a selected bitline coupled to the array of memory cells. A column multiplexer passes a signal on the selected bitline to a sense amplifier input in response to a column enable signal. A multiplexer output conditioner discharges the sense amplifier input and a bitline conditioner precharges and readjusts the selected bitline to a precharge threshold. A sense amplifier produces a data output that is based on the sense amplifier input.
摘要翻译：存储器包括耦合到存储器单元阵列的选定位线。列复用器响应于列使能信号将选定位线上的信号传递到读出放大器输入。多路复用器输出调节器对读出放大器输入进行放电，位线调节器预充电并将所选位线重新调整为预充电阈值。读出放大器产生基于读出放大器输入的数据输出。

5. 发明授权

US06385021B1 Electrostatic discharge (ESD) protection circuit 有权
标题翻译：静电放电（ESD）保护电路
公开(公告)号：US06385021B1
公开(公告)日：2002-05-07
申请号：US09546601
申请日：2000-04-10
申请人： Fujio Takeda , James W. Miller
发明人： Fujio Takeda , James W. Miller
IPC分类号： H02H322
CPC分类号： H01L27/0248 , H01L27/0266
摘要： An ESD protection circuit (39) coupled to each of a plurality of I/O circuits (30, 32, 36) of an integrated circuit (31) is disclosed. The ESD protection circuit includes a MOSFET transistor (40) to provide primary ESD protection on occurrence of an ESD event. In one embodiment, the control electrode of the MOSFET transistor is coupled to a first buffer circuit (42). Integrated circuit (31) includes a remote trigger circuit (37) coupled to the ESD protection circuits via a trigger bus (47). The individual ESD protection circuits operate in parallel to provide ESD protection to the I/O circuits (30, 32, and 36) upon occurrence of an ESD event.
摘要翻译：公开了一种耦合到集成电路（31）的多个I / O电路（30,32,36）中的每一个的ESD保护电路（39）。 ESD保护电路包括MOSFET晶体管（40），用于在发生ESD事件时提供主要的ESD保护。在一个实施例中，MOSFET晶体管的控制电极耦合到第一缓冲电路（42）。集成电路（31）包括经由触发总线（47）耦合到ESD保护电路的远程触发电路（37）。各个ESD保护电路并联工作，以在ESD事件发生时向I / O电路（30,32和36）提供ESD保护。

6. 发明授权

US07359254B2 Controller for controlling a source current to a memory cell, processing system and methods for use therewith 有权
标题翻译：用于控制到存储器单元的源电流的控制器，处理系统和与其一起使用的方法
公开(公告)号：US07359254B2
公开(公告)日：2008-04-15
申请号：US11249963
申请日：2005-10-13
申请人： Fujio Takeda
发明人： Fujio Takeda
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A controller for controlling a source current of a memory cell for use in a static random access memory (SRAM) includes a bias generator for supplying a bias current to the memory cell. A read current generator controls the source current to the memory cell to a read current state when a column containing the memory cell is selected.
摘要翻译：用于控制用于静态随机存取存储器（SRAM）的存储单元的源电流的控制器包括用于向存储单元提供偏置电流的偏置发生器。当选择包含存储单元的列时，读取电流发生器将存储器单元的源电流控制到读取当前状态。

7. 发明授权

US06459325B1 Output buffer having a pre-driver transition controller 失效
标题翻译：输出缓冲器具有预驱动器转换控制器
公开(公告)号：US06459325B1
公开(公告)日：2002-10-01
申请号：US09832149
申请日：2001-04-11
申请人： Geoffrey B. Hall , Fujio Takeda , Michael Priel
发明人： Geoffrey B. Hall , Fujio Takeda , Michael Priel
IPC分类号： H03K1716
CPC分类号： H03K17/163 , H03K4/00 , H03K17/6872
摘要： An output buffer (100) has a pre-driver circuit (120) for controlling a voltage transition of an output signal from an output driver transistor (150). The pre-driver circuit (120) provides an input that slightly leads the gate voltage of the output driver transistor (150). The pre-driver circuit (120) includes a configurable resistance circuit (480) that provides one resistance value at the start of a signal transition and provides another resistance value near the end of the signal transition. A threshold detector (470) senses a voltage level of the input signal and switches from one resistance value to the other resistance value when the input signal crosses a predetermined voltage.
摘要翻译：输出缓冲器（100）具有用于控制来自输出驱动晶体管（150）的输出信号的电压转换的预驱动电路（120）。预驱动器电路（120）提供稍微导致输出驱动晶体管（150）的栅极电压的输入。预驱动器电路（120）包括在信号转换开始时提供一个电阻值的可配置电阻电路（480），并且在信号转换结束附近提供另一个电阻值。当输入信号越过预定电压时，阈值检测器（470）感测输入信号的电压电平并从一个电阻值切换到另一个电阻值。

8. 发明授权

US06327126B1 Electrostatic discharge circuit 有权
标题翻译：静电放电电路
公开(公告)号：US06327126B1
公开(公告)日：2001-12-04
申请号：US09494055
申请日：2000-01-28
申请人： James W. Miller , Michael G. Khazhinsky , Geoffrey B. Hall , Jose A. Camarena , Joseph Chan , Fujio Takeda
发明人： James W. Miller , Michael G. Khazhinsky , Geoffrey B. Hall , Jose A. Camarena , Joseph Chan , Fujio Takeda
IPC分类号： H02H900
CPC分类号： H01L27/0251
摘要： A circuit (600) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (600) includes cascoded NMOSFETs (614, 616), with the upper NMOSFET (614) connected to voltage divider circuitry (628). The voltage divider circuitry (628) provides a first bias voltage to the gate of the upper NMOSFET (614) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately ½ of the drain voltage of the upper NMOSFET (614). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.
摘要翻译：电路（600）在ESD事件期间为集成电路中的内部元件提供静电放电（ESD）保护。电路（600）包括级联的NMOSFET（614,616），其中上部NMOSFET（614）连接到分压器电路（628）。分压器电路（628）在ESD事件期间向上NMOSFET（614）的栅极提供第一偏置电压，并在正常操作期间提供第二偏置电压。优选地，第一偏置电压约为上部NMOSFET（614）的漏极电压的1/2。在这些偏置条件下，级联的NMOSFET表现出用于启动寄生横向双极传导的最大电压阈值。

9. 发明授权

US6021072A Method and apparatus for precharging bitlines in a nonvolatile memory 失效
标题翻译：用于在非易失性存储器中预充电位线的方法和装置
公开(公告)号：US6021072A
公开(公告)日：2000-02-01
申请号：US123927
申请日：1998-07-27
申请人： Fujio Takeda , Steve Vu
发明人： Fujio Takeda , Steve Vu
IPC分类号： G11C7/12 , G11C7/00
CPC分类号： G11C7/12
摘要： A method for precharging a selected bitline (20) in a nonvolatile memory array using a boost circuit (54) in parallel to a pull-up device (22) for biasing the bitline. The boost circuit (54) is controlled by a pulse signal (26). One embodiment uses a regulator circuit (56) to isolate the boost circuit (54) from the bitline when the bitline voltage exceeds a threshold voltage level. The regulator triggers a delay circuit (58) which is coupled to a sense amplifier (60). The delay circuit (58) then defers activation of the sense amplifier (60) until the voltage on the selected bitline (20) is below a sense amplifier threshold voltage level.
摘要翻译：一种用于使用与用于偏置位线的上拉装置（22）并联的升压电路（54）对非易失性存储器阵列中的选定位线（20）进行预充电的方法。升压电路（54）由脉冲信号（26）控制。当位线电压超过阈值电压电平时，一个实施例使用调节器电路（56）将升压电路（54）与位线隔离。调节器触发延迟电路（58），该延迟电路耦合到读出放大器（60）。延迟电路（58）然后延迟读出放大器（60）的激活，直到所选位线（20）上的电压低于读出放大器阈值电压电平。

10. 发明申请

US20150153811A1 PROCESSING SYSTEM WITH LOW POWER WAKE-UP PAD 有权
标题翻译：具有低功率唤醒垫的加工系统
公开(公告)号：US20150153811A1
公开(公告)日：2015-06-04
申请号：US14093473
申请日：2013-11-30
申请人： DZUNG T. TRAN , RISHI BHOOSHAN , RAKESH PANDEY , FUJIO TAKEDA
发明人： DZUNG T. TRAN , RISHI BHOOSHAN , RAKESH PANDEY , FUJIO TAKEDA
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/3287 , H01L27/0222 , H01L29/0611 , H01L29/78609 , Y02D10/171
摘要： An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.
摘要翻译：集成电路包括输入/输出焊盘，输入电路和输出电路。输入电路耦合到输入/输出焊盘，该输入/输出焊盘接收包括唤醒信号的输入信号，该唤醒信号指示集成电路何时从掉电模式切换到活动模式。输出电路耦合到输入/输出焊盘，该输入/输出焊盘向输入/输出焊盘提供输出信号。输出电路包括在阱中的第一P沟道晶体管，其具有耦合到输入/输出焊盘的漏极以及耦合到电源端子的源极。电源端子在活动模式期间接收第一电源电压，并且在掉电模式期间与任何电源解耦。响应于唤醒信号，阱被耦合到唤醒信号，该唤醒信号指示从掉电模式到活动模式的改变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式