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1. 发明授权

US6021072A Method and apparatus for precharging bitlines in a nonvolatile memory 失效
标题翻译：用于在非易失性存储器中预充电位线的方法和装置
公开(公告)号：US6021072A
公开(公告)日：2000-02-01
申请号：US123927
申请日：1998-07-27
申请人： Fujio Takeda , Steve Vu
发明人： Fujio Takeda , Steve Vu
IPC分类号： G11C7/12 , G11C7/00
CPC分类号： G11C7/12
摘要： A method for precharging a selected bitline (20) in a nonvolatile memory array using a boost circuit (54) in parallel to a pull-up device (22) for biasing the bitline. The boost circuit (54) is controlled by a pulse signal (26). One embodiment uses a regulator circuit (56) to isolate the boost circuit (54) from the bitline when the bitline voltage exceeds a threshold voltage level. The regulator triggers a delay circuit (58) which is coupled to a sense amplifier (60). The delay circuit (58) then defers activation of the sense amplifier (60) until the voltage on the selected bitline (20) is below a sense amplifier threshold voltage level.
摘要翻译：一种用于使用与用于偏置位线的上拉装置（22）并联的升压电路（54）对非易失性存储器阵列中的选定位线（20）进行预充电的方法。升压电路（54）由脉冲信号（26）控制。当位线电压超过阈值电压电平时，一个实施例使用调节器电路（56）将升压电路（54）与位线隔离。调节器触发延迟电路（58），该延迟电路耦合到读出放大器（60）。延迟电路（58）然后延迟读出放大器（60）的激活，直到所选位线（20）上的电压低于读出放大器阈值电压电平。

2. 发明授权

US09547623B2 Flexible memory interface system for independently processing different portions of an instruction 有权
标题翻译：灵活的存储器接口系统，用于独立处理指令的不同部分
公开(公告)号：US09547623B2
公开(公告)日：2017-01-17
申请号：US10865585
申请日：2004-06-10
申请人： Steve Vu , Jean Charles Pina
发明人： Steve Vu , Jean Charles Pina
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G06F13/4234 , G06F13/1668 , G06F2213/0038
摘要： A flexible memory interface system includes a control module, instruction memory, a command processing unit, an address processing unit, and a data processing unit. The control module controls storing and retrieving of a command portion, an addressing portion, and data of an instruction to access memory to and from the instruction memory and the command processing unit, the address processing unit, and the data processing unit, respectively. The command processing unit is operably coupled to process a command portion of an instruction to access memory. The address processing unit is operably coupled to process an addressing portion of the instruction to access the memory. The data processing unit is operably coupled to process data conveyance to or from the external memory based on the instruction to access the memory.
摘要翻译：灵活的存储器接口系统包括控制模块，指令存储器，命令处理单元，地址处理单元和数据处理单元。控制模块控制命令部分，寻址部分的存储和获取，以及分别向指令存储器和命令处理单元，地址处理单元和数据处理单元访问存储器的指令的数据。命令处理单元可操作地耦合以处理访问存储器的指令的命令部分。地址处理单元可操作地耦合以处理指令的寻址部分以访问存储器。数据处理单元可操作地耦合以基于访问存储器的指令来处理到外部存储器或从外部存储器传送数据。

3. 发明申请

US20050005078A1 Flexible memory interface system 有权
标题翻译：灵活的内存接口系统
公开(公告)号：US20050005078A1
公开(公告)日：2005-01-06
申请号：US10865585
申请日：2004-06-10
申请人： Steve Vu , Jean Pina
发明人： Steve Vu , Jean Pina
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42
CPC分类号： G06F13/4234 , G06F13/1668 , G06F2213/0038
摘要： A flexible memory interface system includes a control module, instruction memory, a command processing unit, an address processing unit, and a data processing unit. The control module controls storing and retrieving of a command portion, an addressing portion, and data of an instruction to access memory to and from the instruction memory and the command processing unit, the address processing unit, and the data processing unit, respectively. The command processing unit is operably coupled to process a command portion of an instruction to access memory. The address processing unit is operably coupled to process an addressing portion of the instruction to access the memory. The data processing unit is operably coupled to process data conveyance to or from the external memory based on the instruction to access the memory.
摘要翻译：灵活的存储器接口系统包括控制模块，指令存储器，命令处理单元，地址处理单元和数据处理单元。控制模块控制命令部分，寻址部分的存储和获取，以及分别向指令存储器和命令处理单元，地址处理单元和数据处理单元访问存储器的指令的数据。命令处理单元可操作地耦合以处理访问存储器的指令的命令部分。地址处理单元可操作地耦合以处理指令的寻址部分以访问存储器。数据处理单元可操作地耦合以基于访问存储器的指令来处理到外部存储器或从外部存储器传送数据。

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