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1. 发明授权

US09196598B1 Semiconductor device having power distribution using bond wires 有权
标题翻译：具有使用接合线的配电的半导体装置
公开(公告)号：US09196598B1
公开(公告)日：2015-11-24
申请号：US14302425
申请日：2014-06-12
申请人： Shailesh Kumar , Rishi Bhooshan , Vikas Garg , Chetan Verma , Navas Khan Oratti Kalandar
发明人： Shailesh Kumar , Rishi Bhooshan , Vikas Garg , Chetan Verma , Navas Khan Oratti Kalandar
IPC分类号： H01L23/48 , H01L23/00
CPC分类号： H01L24/49 , H01L24/48 , H01L2224/05554 , H01L2224/4554 , H01L2224/4813 , H01L2224/4911 , H01L2224/4917 , H01L2924/00014 , H01L2924/30101 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.
摘要翻译：半导体器件使用绝缘接合线来将设备周边上的外围电源和接地焊盘连接到位于器件的集成电路管芯的内部区域上的阵列电源和接地焊盘。电源和接地电压使用垂直通孔从阵列接合焊盘传送到一个或多个对应的内部配电层。接合线连接形成构成网格电网的行的行和列，其减小了半导体器件的IR降。

2. 发明申请

US20150153811A1 PROCESSING SYSTEM WITH LOW POWER WAKE-UP PAD 有权
标题翻译：具有低功率唤醒垫的加工系统
公开(公告)号：US20150153811A1
公开(公告)日：2015-06-04
申请号：US14093473
申请日：2013-11-30
申请人： DZUNG T. TRAN , RISHI BHOOSHAN , RAKESH PANDEY , FUJIO TAKEDA
发明人： DZUNG T. TRAN , RISHI BHOOSHAN , RAKESH PANDEY , FUJIO TAKEDA
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/3287 , H01L27/0222 , H01L29/0611 , H01L29/78609 , Y02D10/171
摘要： An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.
摘要翻译：集成电路包括输入/输出焊盘，输入电路和输出电路。输入电路耦合到输入/输出焊盘，该输入/输出焊盘接收包括唤醒信号的输入信号，该唤醒信号指示集成电路何时从掉电模式切换到活动模式。输出电路耦合到输入/输出焊盘，该输入/输出焊盘向输入/输出焊盘提供输出信号。输出电路包括在阱中的第一P沟道晶体管，其具有耦合到输入/输出焊盘的漏极以及耦合到电源端子的源极。电源端子在活动模式期间接收第一电源电压，并且在掉电模式期间与任何电源解耦。响应于唤醒信号，阱被耦合到唤醒信号，该唤醒信号指示从掉电模式到活动模式的改变。

3. 发明申请

US20140353849A1 SYSTEM FOR PREVENTING TAMPERING WITH INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路防止篡改的系统
公开(公告)号：US20140353849A1
公开(公告)日：2014-12-04
申请号：US13905150
申请日：2013-05-30
申请人： Mohit Arora , Prashant Bhargava , Rishi Bhooshan
发明人： Mohit Arora , Prashant Bhargava , Rishi Bhooshan
IPC分类号： H01L23/00
CPC分类号： G06F21/86 , G06F2221/2143 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.
摘要翻译：用于产生表示篡改集成电路（IC）的一个或多个电路的篡改检测信号的系统包括篡改检测模块和连接到篡改检测模块并且以绕组配置布置以形成线网的线对。线网放置在与电路预定距离的位置。篡改检测模块生成并提供串行比特流到线对，用于通过外部探针检测金属丝网中的突破。

4. 发明申请

US20140332811A1 SEMICONDUCTOR DEVICE WITH BOND AND PROBE PADS 审中-公开
标题翻译：具有粘结和探针垫的半导体器件
公开(公告)号：US20140332811A1
公开(公告)日：2014-11-13
申请号：US13892297
申请日：2013-05-12
申请人： Naveen Kumar , Gurinder Singh Baghria , Rishi Bhooshan , Jesse Phou
发明人： Naveen Kumar , Gurinder Singh Baghria , Rishi Bhooshan , Jesse Phou
IPC分类号： H01L21/66
CPC分类号： H01L22/32 , H01L24/05 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/04042 , H01L2224/05082 , H01L2224/05147 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/06135 , H01L2224/32245 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor die has an active face with an arrangement of I/O pads around its edges. The I/O pads include bond pads and probe pads. Two types of I/O pads are provided and the two types of pads are arranged in a staggered arrangement around the edges of the die. The first type of I/O pad has bond pads that are spaced from the probe pads and connected with an interconnecting member. The second type of I/O pads has bond pads that are adjacent to and abutting probe pads. Providing two types of I/O pads and the staggered arrangement of the I/O pads reduces the area of the I/O pads and underlying I/O regions, which saves core area of the die.
摘要翻译：半导体管芯具有在其边缘周围布置有I / O焊盘的主动面。 I / O焊盘包括焊盘和探针焊盘。提供两种类型的I / O焊盘，并且两种类型的焊盘以围绕模具的边缘的交错布置布置。第一类型的I / O焊盘具有与探针焊盘间隔开并与互连构件连接的接合焊盘。第二类型的I / O焊盘具有与探针焊盘相邻并邻接的焊盘。提供两种类型的I / O焊盘和I / O焊盘的交错排列减少了I / O焊盘和底层I / O区域的面积，从而节省了芯片的核心面积。

5. 发明申请

US20070094630A1 Power grid design in an integrated circuit 审中-公开
标题翻译：集成电路中的电网设计
公开(公告)号：US20070094630A1
公开(公告)日：2007-04-26
申请号：US11163520
申请日：2005-10-21
申请人： Rishi Bhooshan
发明人： Rishi Bhooshan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F2217/78
摘要： An aspect of the present invention computationally determines the metal density of each metal layer supporting a power grid structure providing power to the elements of an integrated circuits. The metal densities are computed such that the power grid would support aggregate power and IR drop constraints. The metal densities thus computed are provided as inputs to a router block, which places the grid structure along with the signal paths on the layout of the eventual integrated circuit sought to be fabricated. Due to the computation of the metal densities upfront and providing to the router block, the iterative design of the IC might be avoided.
摘要翻译：本发明的一个方面计算地确定支持向集成电路的元件提供电力的电网结构的每个金属层的金属密度。计算金属密度，使得电网将支持聚集功率和IR下降约束。这样计算的金属密度被提供给路由器块的输入，路由器块将网格结构与信号路径一起放置在想要制造的最终集成电路的布局上。由于前期的金属密度的计算和提供给路由器块，可以避免IC的迭代设计。

6. 发明申请

US20150221592A1 SEMICONDUCTOR DEVICE WITH PACKAGE-LEVEL DECOUPLING CAPACITORS FORMED WITH BOND WIRES 审中-公开
标题翻译：具有捆绑线形式的封装级解耦电容器的半导体器件
公开(公告)号：US20150221592A1
公开(公告)日：2015-08-06
申请号：US14170651
申请日：2014-02-03
申请人： Chetan Verma , Rishi Bhooshan , Vikas Garg , Shailesh Kumar , Navas Khan Oratti Kalandar
发明人： Chetan Verma , Rishi Bhooshan , Vikas Garg , Shailesh Kumar , Navas Khan Oratti Kalandar
IPC分类号： H01L23/522 , H01L23/00
CPC分类号： H01L24/49 , H01L23/5223 , H01L24/48 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/48091 , H01L2224/48101 , H01L2224/4813 , H01L2224/48464 , H01L2224/4903 , H01L2224/49052 , H01L2224/49097 , H01L2224/4911 , H01L2224/49111 , H01L2224/49175 , H01L2224/49431 , H01L2924/00014 , H01L2924/1205 , H01L2924/14 , H01L2924/181 , H01L2924/19104 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A decoupling capacitor (decap) for circuitry (e.g., an I/O interface) in a semiconductor die is formed using one or more pairs of (parallel) bond wires wire-bonded to bond pads on a top surface of the die. Depending on the implementation, the pairs of bond wires may be horizontally or vertically aligned and may be bonded to I/O and/or array bond pads.
摘要翻译：用半导体管芯中的电路（例如，I / O接口）的去耦电容器（decap）是使用一对或多对引线键合到管芯顶表面上的接合焊盘的（平行）接合线形成的。根据实施方式，这对接合线可以是水平或垂直对准的并且可以结合到I / O和/或阵列接合焊盘。

7. 发明授权

US09147656B1 Semiconductor device with improved shielding 有权
标题翻译：半导体器件具有改进的屏蔽
公开(公告)号：US09147656B1
公开(公告)日：2015-09-29
申请号：US14328711
申请日：2014-07-11
申请人： Sumit Varshney , Rishi Bhooshan , Meng Kong Lye , Chetan Verma
发明人： Sumit Varshney , Rishi Bhooshan , Meng Kong Lye , Chetan Verma
IPC分类号： H01L23/495 , H01L23/552 , H01L23/522
CPC分类号： H01L23/49558 , H01L23/49541 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/04042 , H01L2224/32245 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.
摘要翻译：一种用于半导体器件的屏蔽结构。屏蔽结构具有带指状物的基座，其尺寸和形状被设计成在相邻引线对之间的空间内延伸。基座在芯片标记和引线之间的空间内延伸。屏蔽结构进一步连接到一个接地引线。

8. 发明授权

US08896086B1 System for preventing tampering with integrated circuit 有权
标题翻译：防止篡改集成电路的系统
公开(公告)号：US08896086B1
公开(公告)日：2014-11-25
申请号：US13905150
申请日：2013-05-30
申请人： Mohit Arora , Prashant Bhargava , Rishi Bhooshan
发明人： Mohit Arora , Prashant Bhargava , Rishi Bhooshan
IPC分类号： H01L23/02 , H01L23/00
CPC分类号： G06F21/86 , G06F2221/2143 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.
摘要翻译：用于产生表示篡改集成电路（IC）的一个或多个电路的篡改检测信号的系统包括篡改检测模块和连接到篡改检测模块并且以绕组配置布置以形成线网的线对。线网放置在与电路预定距离的位置。篡改检测模块生成并提供串行比特流到线对，用于通过外部探针检测金属丝网中的突破。

9. 发明授权

US07315992B2 Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs 有权
标题翻译：集成电路（IC）设计的电迁移（EM）和电压（IR）下降分析
公开(公告)号：US07315992B2
公开(公告)日：2008-01-01
申请号：US10710693
申请日：2004-07-29
申请人： Rishi Bhooshan , Sampath Kuve , Venugopal Puvvada
发明人： Rishi Bhooshan , Sampath Kuve , Venugopal Puvvada
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migration) violations to be determined. Another features improves such analysis in case of memory modules. One more feature enables determination of whether sufficient voltages will be applied to program efuses in a module containing the efuses. Yet another feature enables the signal characteristics of an output path/pin to be determined to check for any EM violations.
摘要翻译：基于对应的布局文件执行模块的近似分析，同时要比执行模块或集成电路设计的晶体管级仿真要少的计算。一个特征可以确定IR /电压降和EM（电迁移）违规。在内存模块的情况下，另一个特性改进了这种分析。还有一个功能可以确定是否有足够的电压施加到包含efuses的模块中的程序efuses。另一个特征使得能够确定输出路径/引脚的信号特性来检查是否存在EM违规。

10. 发明申请

US20150214167A1 SEMICONDUCTOR DIE WITH VARIABLE LENGTH BOND PAD 审中-公开
标题翻译：具有可变长度粘结垫的SEMICONDUCTOR DIE
公开(公告)号：US20150214167A1
公开(公告)日：2015-07-30
申请号：US14164249
申请日：2014-01-26
申请人： Rishi Bhooshan , Sachin Kalra , Rakesh Pandey , Dzung T. Tran
发明人： Rishi Bhooshan , Sachin Kalra , Rakesh Pandey , Dzung T. Tran
IPC分类号： H01L23/00
CPC分类号： H01L24/06 , H01L24/05 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/0603 , H01L2224/06151 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor die has elongate, adjacent external interface cells that form an interface cell row. Each of the external interface cells provides an external interface for a circuit node of the die. Bond pads are disposed on a surface of the die, with each of the bond pads being electrically connected to a directly underlying one of the interface cells of the interface cell row. Each of the bond pads has a longitudinal axis aligned with a lengthwise axis of its respective directly underlying interface cell. Each of the bond pads also has a multiple potential wire bond site locations along its respective longitudinal axes.
摘要翻译：半导体管芯具有形成界面单元行的细长的相邻外部接口单元。每个外部接口单元为芯片的电路节点提供外部接口。接合焊盘设置在管芯的表面上，其中每个接合焊盘电连接到接口单元行的接口单元的直接下面的一个。每个接合焊盘具有与其相应的直接下面的接口单元的纵向轴线对准的纵向轴线。每个接合焊盘还沿着其各自的纵向轴线具有多个潜在的焊线位置位置。

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