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1. 发明授权

US07525150B2 High voltage double diffused drain MOS transistor with medium operation voltage 有权
标题翻译：具有中等工作电压的高压双扩散漏极MOS晶体管
公开(公告)号：US07525150B2
公开(公告)日：2009-04-28
申请号：US10819527
申请日：2004-04-07
申请人： Fu-Hsin Chen , Yi-Chun Lin , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Yi-Chun Lin , Ruey-Hsin Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/66659 , H01L21/823418 , H01L29/0692 , H01L29/0847 , H01L29/7835
摘要： A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low and higher operation transistor devices. The second diffusion region of the DDD is self-aligned to the spacer on the sidewalls of the gate and gate dielectric, so that the transistor size may be decreased.
摘要翻译：一种在半导体晶片上制造具有中等工作电压的高压MOS晶体管的方法。晶体管具有双扩散漏极（DDD）和诸如6至10伏特的中等操作电压，这对于具有低和高操作晶体管器件的应用是有利的。 DDD的第二扩散区域与栅极和栅极电介质的侧壁上的间隔物自对准，使得晶体管尺寸可能降低。

2. 发明申请

US20050227448A1 High voltage double diffused drain MOS transistor with medium operation voltage 有权
标题翻译：具有中等工作电压的高压双扩散漏极MOS晶体管
公开(公告)号：US20050227448A1
公开(公告)日：2005-10-13
申请号：US10819527
申请日：2004-04-07
申请人： Fu-Hsin Chen , Yi-Chun Lin , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Yi-Chun Lin , Ruey-Hsin Liu
IPC分类号： H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/823418 , H01L29/0692 , H01L29/0847 , H01L29/7835
摘要： A method of fabricating a high voltage MOS transistor with a medium operation voltage on a semiconductor wafer. The transistor has a double diffused drain (DDD) and a medium operation voltage such as 6 to 10 volts, which is advantageous for applications having both low and higher operation transistor devices. The second diffusion region of the DDD is self-aligned to the spacer on the sidewalls of the gate and gate dielectric, so that the transistor size may be decreased.
摘要翻译：一种在半导体晶片上制造具有中等工作电压的高压MOS晶体管的方法。晶体管具有双扩散漏极（DDD）和诸如6至10伏特的中等操作电压，这对于具有低和高操作晶体管器件的应用是有利的。 DDD的第二扩散区域与栅极和栅极电介质的侧壁上的间隔物自对准，使得晶体管尺寸可能降低。

3. 发明授权

US07525155B2 High voltage transistor structure for semiconductor device 有权
标题翻译：半导体器件用高压晶体管结构
公开(公告)号：US07525155B2
公开(公告)日：2009-04-28
申请号：US11387573
申请日：2006-03-23
申请人： Fu-Hsin Chen , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Ruey-Hsin Liu
IPC分类号： H01L29/94 , H01L29/74
CPC分类号： H01L29/66659 , H01L29/0692 , H01L29/7835
摘要： A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped region is formed within the first doped region. A gate-side boundary of the second doped region is separated from a closest edge of the gate electrode by a first spaced distance. The gate-side boundary of the second doped region is separated from a closest edge of the spacer by a second spaced distance. The first spaced distance is greater than the second spaced distance. An isolation-side boundary of the second doped region may be separated from an adjacent isolation structure by a third spaced distance.
摘要翻译：高压MOS晶体管具有热驱动的第一掺杂区域和形成双扩散漏极结构的第二掺杂区域。第一掺杂区域的边界被分级。第一掺杂区的栅极侧边界在栅电极的一部分的横向下方延伸。第二掺杂区域形成在第一掺杂区域内。第二掺杂区域的栅极侧边界与栅电极的最近边缘隔开第一间隔距离。第二掺杂区域的栅极侧边界与间隔物的最近边缘隔开第二间隔距离。第一间隔距离大于第二间隔距离。第二掺杂区域的隔离侧边界可以与相邻隔离结构隔开第三间隔距离。

4. 发明授权

US07196375B2 High-voltage MOS transistor 有权
标题翻译：高压MOS晶体管
公开(公告)号：US07196375B2
公开(公告)日：2007-03-27
申请号：US10801234
申请日：2004-03-16
申请人： Fu-Hsin Chen , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Ruey-Hsin Liu
IPC分类号： H01L29/76
CPC分类号： H01L29/66575 , H01L29/66659
摘要： A method for fabricating a high-voltage MOS transistor. A first doping region with a first dosage is formed in a substrate. A gate structure is formed overlying the substrate and partially covers the first doping region. The substrate is ion implanted using the gate structure as a mask to simultaneously form a second doping region with a second dosage within the first doping region to serve as a drain region and form a third doping region with the second dosage in the substrate to serve as a source region. A channel region is formed in the substrate between the first and third doping regions when the high-voltage MOS transistor is turned on to pass current between the source and drain regions, where a resistance per unit length of the channel region is substantially equal to that of the first doping region. A high-voltage MOS transistor is also disclosed.
摘要翻译：一种用于制造高压MOS晶体管的方法。在衬底中形成具有第一剂量的第一掺杂区域。栅极结构形成在衬底上并部分地覆盖第一掺杂区域。使用栅极结构作为掩模离子注入衬底，以在第一掺杂区域内同时形成具有第二剂量的第二掺杂区域，以用作漏极区域，并形成第二掺杂区域，第二掺杂区域在衬底中用作第二掺杂区域，以用作源区域。当高电压MOS晶体管导通时，沟道区形成在第一和第三掺杂区之间的衬底中，以在源极和漏极区之间传导电流，其中沟道区的每单位长度的电阻基本上等于的第一个掺杂区域。还公开了高压MOS晶体管。

5. 发明申请

US20090001462A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20090001462A1
公开(公告)日：2009-01-01
申请号：US12205961
申请日：2008-09-08
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

6. 发明授权

US07045414B2 Method of fabricating high voltage transistor 有权
标题翻译：制造高压晶体管的方法
公开(公告)号：US07045414B2
公开(公告)日：2006-05-16
申请号：US10723771
申请日：2003-11-26
申请人： Fu-Hsin Chen , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Ruey-Hsin Liu
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L29/66659 , H01L29/0692 , H01L29/7835
摘要： A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped region is formed within the first doped region. A gate-side boundary of the second doped region is separated from a closest edge of the gate electrode by a first spaced distance. The gate-side boundary of the second doped region is separated from a closest edge of the spacer by a second spaced distance. The first spaced distance is greater than the second spaced distance. An isolation-side boundary of the second doped region may be separated from an adjacent isolation structure by a third spaced distance.
摘要翻译：高压MOS晶体管具有热驱动的第一掺杂区域和形成双扩散漏极结构的第二掺杂区域。第一掺杂区域的边界被分级。第一掺杂区的栅极侧边界在栅电极的一部分的横向下方延伸。第二掺杂区域形成在第一掺杂区域内。第二掺杂区域的栅极侧边界与栅电极的最近边缘隔开第一间隔距离。第二掺杂区域的栅极侧边界与间隔物的最近边缘隔开第二间隔距离。第一间隔距离大于第二间隔距离。第二掺杂区域的隔离侧边界可以与相邻隔离结构隔开第三间隔距离。

7. 发明授权

US08389341B2 Lateral power MOSFET with high breakdown voltage and low on-resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US08389341B2
公开(公告)日：2013-03-05
申请号：US13175246
申请日：2011-07-01
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

8. 发明申请

US20120003803A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20120003803A1
公开(公告)日：2012-01-05
申请号：US13175246
申请日：2011-07-01
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

9. 发明申请

US20060163626A1 High voltage transistor structure for semiconductor device 有权
公开(公告)号：US20060163626A1
公开(公告)日：2006-07-27
申请号：US11387573
申请日：2006-03-23
申请人： Fu-Hsin Chen , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Ruey-Hsin Liu
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66659 , H01L29/0692 , H01L29/7835
摘要： A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped region is formed within the first doped region. A gate-side boundary of the second doped region is separated from a closest edge of the gate electrode by a first spaced distance. The gate-side boundary of the second doped region is separated from a closest edge of the spacer by a second spaced distance. The first spaced distance is greater than the second spaced distance. An isolation-side boundary of the second doped region may be separated from an adjacent isolation structure by a third spaced distance.

10. 发明申请

US20050205926A1 High-voltage MOS transistor and method for fabricating the same 有权
标题翻译：高压MOS晶体管及其制造方法
公开(公告)号：US20050205926A1
公开(公告)日：2005-09-22
申请号：US10801234
申请日：2004-03-16
申请人： Fu-Hsin Chen , Ruey-Hsin Liu
发明人： Fu-Hsin Chen , Ruey-Hsin Liu
IPC分类号： H01L21/336 , H01L21/822 , H01L29/94
CPC分类号： H01L29/66575 , H01L29/66659
摘要： A method for fabricating a high-voltage MOS transistor. A first doping region with a first dosage is formed in a substrate. A gate structure is formed overlying the substrate and partially covers the first doping region. The substrate is ion implanted using the gate structure as a mask to simultaneously form a second doping region with a second dosage within the first doping region to serve as a drain region and form a third doping region with the second dosage in the substrate to serve as a source region. A channel region is formed in the substrate between the first and third doping regions when the high-voltage MOS transistor is turned on to pass current between the source and drain regions, where a resistance per unit length of the channel region is substantially equal to that of the first doping region. A high-voltage MOS transistor is also disclosed.
摘要翻译：一种用于制造高压MOS晶体管的方法。在衬底中形成具有第一剂量的第一掺杂区域。栅极结构形成在衬底上并部分地覆盖第一掺杂区域。使用栅极结构作为掩模离子注入衬底，以在第一掺杂区域内同时形成具有第二剂量的第二掺杂区域，以用作漏极区域，并形成第二掺杂区域，第二掺杂区域在衬底中用作第二掺杂区域，以用作源区域。当高电压MOS晶体管导通时，沟道区形成在第一和第三掺杂区之间的衬底中，以在源极和漏极区之间传导电流，其中沟道区的每单位长度的电阻基本上等于的第一个掺杂区域。还公开了高压MOS晶体管。

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