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1. 发明申请

US20100197098A1 METHOD OF FABRICATING A HIGH PERFORMANCE POWER MOS 有权
标题翻译：制造高性能功率MOS的方法
公开(公告)号：US20100197098A1
公开(公告)日：2010-08-05
申请号：US12757242
申请日：2010-04-09
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.
摘要翻译：制造半导体器件的方法包括在衬底中形成包括第一类掺杂剂的阱区; 在所述阱区中形成包含不同于所述第一类型掺杂剂的第二类型掺杂剂的基极区; 以及在包括第一类型掺杂剂的衬底源极和漏极区域中形成。该方法还包括在衬底上形成横向插入在源区和漏区之间的栅电极; 以及在所述衬底上形成栅极间隔件，所述栅极间隔件横向设置在所述源区域和所述栅电极之间，邻近所述栅电极的一侧并且具有嵌入其中的导电特征。阱区域围绕漏极区域和基极区域，并且基极区域部分地设置在围绕源极区域的栅极电极周围，该源极区域限定栅极电极下方的沟道，其长度基本上小于栅电极的长度的一半。

2. 发明授权

US07723785B2 High performance power MOS structure 有权
标题翻译：高性能功率MOS结构
公开(公告)号：US07723785B2
公开(公告)日：2010-05-25
申请号：US11831689
申请日：2007-07-31
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.
摘要翻译：半导体器件包括设置在衬底中的源区和漏区，其中源区和漏区具有第一类掺杂剂; 形成在所述基板上的栅极电极，横向插入在所述源极和漏极区域之间; 栅极间隔物，设置在所述基板上，并且在所述源极区域和所述栅极电极之间的横向上与所述栅电极的一侧相邻; 以及嵌入栅极间隔物中的导电特征。

3. 发明申请

US20090032868A1 HIGH PERFORMANCE POWER MOS STRUCTURE 有权
标题翻译：高性能功率MOS结构
公开(公告)号：US20090032868A1
公开(公告)日：2009-02-05
申请号：US11831689
申请日：2007-07-31
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A semiconductor device includes a source region and a drain region disposed in a substrate wherein the source and drain regions have a first type of dopant; a gate electrode formed on the substrate interposed laterally between the source and drain regions; a gate spacer disposed on the substrate and laterally between the source region and the gate electrode, adjacent a side of the gate electrode; and a conductive feature embedded in the gate spacer.
摘要翻译：半导体器件包括设置在衬底中的源区和漏区，其中源区和漏区具有第一类掺杂剂; 形成在所述基板上的栅极电极，横向插入在所述源极和漏极区域之间; 栅极间隔物，设置在所述基板上，并且在所述源极区域和所述栅极电极之间的横向上与所述栅电极的一侧相邻; 以及嵌入栅极间隔物中的导电特征。

4. 发明授权

US07888216B2 Method of fabricating a high performance power MOS 有权
标题翻译：制造高性能功率MOS的方法
公开(公告)号：US07888216B2
公开(公告)日：2011-02-15
申请号：US12757242
申请日：2010-04-09
申请人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
发明人： Yu Wen Chen , Fu-Hsin Chen , Tsung-Yi Huang , Yt Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/26586 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/66689 , H01L29/7817
摘要： A method of fabricating a semiconductor device includes forming in the substrate a well region comprising a first type of dopant; forming in the well region a base region comprising a second type of dopant different from the first type of dopant; and forming in the substrate source and drain regions comprising the first type of dopant. The method further includes forming on the substrate a gate electrode interposed laterally between the source and drain regions; and forming on the substrate a gate spacer disposed laterally between the source region and the gate electrode adjacent a side of the gate electrode and having a conductive feature embedded therein. The well region surrounds the drain region and the base region, and the base region is disposed partially underlying the gate electrode surrounding the source region defining a channel under the gate electrode of having a length substantially less than half the length of the gate electrode.
摘要翻译：制造半导体器件的方法包括在衬底中形成包括第一类掺杂剂的阱区; 在所述阱区中形成包含不同于所述第一类型掺杂剂的第二类型掺杂剂的基极区; 以及在包括第一类型掺杂剂的衬底源极和漏极区域中形成。该方法还包括在衬底上形成横向插入在源区和漏区之间的栅电极; 以及在所述衬底上形成栅极间隔件，所述栅极间隔件横向设置在所述源区域和所述栅电极之间，邻近所述栅电极的一侧并且具有嵌入其中的导电特征。阱区域围绕漏极区域和基极区域，并且基极区域部分地设置在围绕源极区域的栅极电极周围，该源极区域限定栅极电极下方的沟道，其长度基本上小于栅电极的长度的一半。

5. 发明授权

US07960786B2 Breakdown voltages of ultra-high voltage devices by forming tunnels 有权
标题翻译：通过形成隧道的超高压装置的击穿电压
公开(公告)号：US07960786B2
公开(公告)日：2011-06-14
申请号：US12170246
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 所述第一导电类型的场环占据所述HVW的顶部部分，其中所述预HVW，所述HVW和所述场环中的至少一个包括至少两个隧道; 在场环上的绝缘区域和HVW的一部分; 在HVW中的漏极区域并且邻近绝缘区域; 绝缘区域的一部分上的栅电极; 以及栅极电极的与漏极区域相反的一侧的源极区域。

6. 发明授权

US07768071B2 Stabilizing breakdown voltages by forming tunnels for ultra-high voltage devices 有权
标题翻译：通过形成超高压设备的隧道来稳定击穿电压
公开(公告)号：US07768071B2
公开(公告)日：2010-08-03
申请号：US12170285
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Puo-Yu Chiang
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Puo-Yu Chiang
IPC分类号： H01L23/62
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW; and a tunnel of the first conductivity type in the pre-HVW and the HVW, and electrically connecting the field ring and the semiconductor substrate.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 第一导电类型的场环占据HVW的顶部; 以及预HVW和HVW中的第一导电类型的隧道，并且电场连接场环和半导体衬底。

7. 发明申请

US20100006935A1 Breakdown Voltages of Ultra-High Voltage Devices By Forming Tunnels 有权
标题翻译：通过形成隧道的超高压器件的故障电压
公开(公告)号：US20100006935A1
公开(公告)日：2010-01-14
申请号：US12170246
申请日：2008-07-09
申请人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
发明人： Eric Huang , Tsung-Yi Huang , Fu-Hsin Chen , Chyi-Chyuan Huang , Chung-Yeh Wu
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/266 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring of the first conductivity type occupying a top portion of the HVW, wherein at least one of the pre-HVW, the HVW, and the field ring comprises at least two tunnels; an insulation region over the field ring and a portion of the HVW; a drain region in the HVW and adjacent the insulation region; a gate electrode over a portion the insulation region; and a source region on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; 所述第一导电类型的场环占据所述HVW的顶部部分，其中所述预HVW，所述HVW和所述场环中的至少一个包括至少两个隧道; 在场环上的绝缘区域和HVW的一部分; 在HVW中的漏极区域并且邻近绝缘区域; 绝缘区域的一部分上的栅电极; 以及栅极电极的与漏极区域相反的一侧的源极区域。

8. 发明申请

US20090001462A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20090001462A1
公开(公告)日：2009-01-01
申请号：US12205961
申请日：2008-09-08
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

9. 发明授权

US08389341B2 Lateral power MOSFET with high breakdown voltage and low on-resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US08389341B2
公开(公告)日：2013-03-05
申请号：US13175246
申请日：2011-07-01
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

10. 发明申请

US20120003803A1 Lateral Power MOSFET with High Breakdown Voltage and Low On-Resistance 有权
标题翻译：具有高击穿电压和低导通电阻的侧向功率MOSFET
公开(公告)号：US20120003803A1
公开(公告)日：2012-01-05
申请号：US13175246
申请日：2011-07-01
申请人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
发明人： Tsung-Yi Huang , Puo-Yu Chiang , Ruey-Hsin Liu , Shun-Liang Hsu , Chyi-Chyuan Huang , Fu-Hsin Chen , Eric Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/42368 , H01L29/66659 , H01L29/7835
摘要： A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.
摘要翻译：半导体结构包括第一导电类型的半导体衬底; 在所述半导体衬底中的预高压阱（预HVW），其中所述预HVW具有与所述第一导电类型相反的第二导电类型; 在HVW之前的高压井（HVW），其中HVW是第二导电类型; HVW中的场环，占据HVW的顶部，其中场环是第一导电类型; 与场环和HVW的一部分接触的绝缘区域; 位于所述绝缘区域上的栅电极; 所述HVW中的漏极区域，其中所述漏极区域是所述第二导电类型; 并且其中所述HVW水平地延伸到所述漏极区域比所述预HVW; 以及与漏极区域相邻并且在与栅极电极相反的一侧的源极区域。

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