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1. 发明授权

US09699014B2 Digital modulation jitter compensation for polar transmitter 有权
公开(公告)号：US09699014B2
公开(公告)日：2017-07-04
申请号：US13412533
申请日：2012-03-05
申请人： Markus Schimper , Franz Kuttner
发明人： Markus Schimper , Franz Kuttner
IPC分类号： H04L27/36
CPC分类号： H04L27/361 , H04L27/367
摘要： This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.

2. 发明授权

US08854127B2 DC-DC converter for envelope tracking 有权
标题翻译：用于包络跟踪的DC-DC转换器
公开(公告)号：US08854127B2
公开(公告)日：2014-10-07
申请号：US13471839
申请日：2012-05-15
申请人： Franz Kuttner
发明人： Franz Kuttner
IPC分类号： H03G3/20
CPC分类号： H02M3/158 , H02M3/157 , H03F1/0227 , H03F1/025
摘要： Embodiments provide a DC-DC converter (DC-DC=direct current to direct current) for envelope tracking. The DC-DC converter includes a digital control stage and a driving stage. The digital control stage is configured to provide a digital control signal based on digital information describing an amplitude of a digital baseband transmit signal. The driving stage is configured to provide a supply voltage for an RF amplifier (RF=radio frequency) based on the digital control signal.
摘要翻译：实施例提供用于包络跟踪的DC-DC转换器（DC-DC =直流电流）。 DC-DC转换器包括数字控制级和驱动级。数字控制级被配置为基于描述数字基带发送信号的幅度的数字信息来提供数字控制信号。驱动级被配置为基于数字控制信号为RF放大器（RF =射频）提供电源电压。

3. 发明申请

US20140146914A1 Digital to Analog Converter Comprising Mixer 有权
标题翻译：数模转换器包括混频器
公开(公告)号：US20140146914A1
公开(公告)日：2014-05-29
申请号：US13688980
申请日：2012-11-29
申请人： Franz Kuttner , Michael Fulde
发明人： Franz Kuttner , Michael Fulde
IPC分类号： H03M1/66 , H04L27/04
CPC分类号： H03M1/66 , H03M1/0624 , H03M1/685
摘要： One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital input signal, and a plurality of cells arranged in rows and columns. Each cell includes a current source. A row decoder and a column decoder provide respective control signals to respective rows and respective columns to selectively couple a number of the current sources to an output of the DAC. The number of current sources which are coupled to the output by the control signals is dependent on the multi-bit digital input signal. At least one of the control signals is modulated based on a local oscillator signal.
摘要翻译：本文描述的一个示例涉及数模转换器（DAC）。 DAC包括被配置为接收多位数字输入信号的数字信号输入和以行和列排列的多个单元。每个单元格包括一个电流源。行解码器和列解码器向相应的行和相应列提供相应的控制信号，以选择性地将多个电流源耦合到DAC的输出。通过控制信号耦合到输出的电流源的数量取决于多位数字输入信号。基于本地振荡器信号调制至少一个控制信号。

4. 发明授权

US08653995B2 Compensation of nonlinearity of single ended digital to analog converters 有权
标题翻译：单端数模转换器的非线性补偿
公开(公告)号：US08653995B2
公开(公告)日：2014-02-18
申请号：US13103917
申请日：2011-05-09
申请人： Franz Kuttner
发明人： Franz Kuttner
IPC分类号： H03M1/66
CPC分类号： H03M1/1057 , H03M1/745
摘要： This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.
摘要翻译：本公开涉及对单端数字模拟电路的当前单元中的电容反馈产生的非线性的补偿。

5. 发明申请

US20120049904A1 Digital Waveform Synthesis 有权
标题翻译：数字波形合成
公开(公告)号：US20120049904A1
公开(公告)日：2012-03-01
申请号：US12862749
申请日：2010-08-24
申请人： Franz KUTTNER , Michael FULDE
发明人： Franz KUTTNER , Michael FULDE
IPC分类号： H03B28/00 , H02J4/00
CPC分类号： G06F1/022 , G06F2101/04 , Y10T307/50
摘要： A circuit is provided with a plurality current cells. The current cells each comprise a main current source and an auxiliary current source coupled in parallel. The main current source supplies a main current to a current output of the current cell, and the auxiliary current source supplies an auxiliary current to the current output of the current cell. The main current sources are weighted according to a first predefined waveform, and the auxiliary current sources are weighted according to a second predefined waveform which is different from the first predefined waveform.
摘要翻译：电路设有多个电流单元。当前单元每个包括并联耦合的主电流源和辅助电流源。主电流源向当前单元的电流输出提供主电流，并且辅助电流源向当前单元的电流输出提供辅助电流。根据第一预定义波形对主电流源进行加权，并且根据与第一预定义波形不同的第二预定义波形对辅助电流源进行加权。

6. 发明申请

US20110043293A1 DeMOS VCO 审中-公开
公开(公告)号：US20110043293A1
公开(公告)日：2011-02-24
申请号：US12543629
申请日：2009-08-19
申请人： Gerhard KNOBLINGER , Marc TIEBOUT , Franz KUTTNER
发明人： Gerhard KNOBLINGER , Marc TIEBOUT , Franz KUTTNER
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1265
摘要： The present disclosure relates voltage controlled oscillators (VCO) and digitally controlled oscillators (DCO). In one implementation, a VCO is implemented with drain extended MOS transistors (DeMOS). In another implementation, a DCO is implemented with DeMOS devices.
摘要翻译：本公开涉及压控振荡器（VCO）和数字控制振荡器（DCO）。在一个实现中，使用漏极扩展MOS晶体管（DeMOS）实现VCO。在另一个实现中，使用DeMOS设备实现DCO。

7. 发明申请

US20070046518A1 Digital-analog converter and digital-analog conversion method 有权
公开(公告)号：US20070046518A1
公开(公告)日：2007-03-01
申请号：US10564312
申请日：2004-07-07
申请人： Franz Kuttner
发明人： Franz Kuttner
IPC分类号： H03M1/66
CPC分类号： H03M1/066 , H03M1/685 , H03M3/502
摘要： The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the digital input data (11) on the basis of a predetermined algorithm to determine an initial cell and a final cell in the array arrangement (22), between which there are situated cells (24) with energy sources (30) to be activated; a decoder device (16) for decoding the at least two digital output data items (13, 14) from the DEM device (10) into actuation signals (17, 17′, 18, 18′, 19, 19′ 20, 20′, 21, 21′) in order to activate the cells (24) which are to be activated; and an array arrangement (22) of cells (23) for outputting at least one quantized analog signal (25, 25′) on the basis of the actuation signals (17, 17′, 18, 18′, 19, 19′ 20, 20′, 21, 21′). The present invention likewise provides a method for digital-analog conversion.

8. 发明授权

US06803870B2 Procedure and device for analog-to-digital conversion 有权
标题翻译：用于模数转换的程序和设备
公开(公告)号：US06803870B2
公开(公告)日：2004-10-12
申请号：US10642730
申请日：2003-08-19
申请人： Franz Kuttner
发明人： Franz Kuttner
IPC分类号： H03M112
CPC分类号： H03M3/39 , H03M3/424 , H03M3/426 , H03M3/436
摘要： During A/D conversion of time-discrete analog input values, a quantizer is used in which an analog quantization error is obtained after every conversion. The quantization error is stored in a buffer, and fed back through a subtracter to at least one input value of a subsequent conversion. The quantizer has a conversion frequency, which is more than double the maximum frequency contained in input values, so the conversion operates in an oversampling mode. During feedback the quantization errors of several conversions, prior to a varying number of conversions, are preferably fed back to an input value. The invention can be used with all conventional quantizers, for which an analog quantization error can be obtained, so it is possible through a noise shaping procedure to shift quantization noise into higher-frequency spectral ranges to improve the signal-to-noise ratio or reduce the quantization noise in a useful spectral range.
摘要翻译：在时间离散模拟输入值的A / D转换期间，使用量化器，其中在每次转换之后获得模拟量化误差。量化误差被存储在缓冲器中，并通过减法器反馈到后续转换的至少一个输入值。量化器具有转换频率，其大小是输入值中包含的最大频率的两倍，因此转换工作在过采样模式。在反馈期间，在不同数目的转换之前的几个转换的量化误差优选地被反馈到输入值。本发明可以与可以获得模拟量化误差的所有常规量化器一起使用，因此可以通过噪声整形过程将量化噪声转换为更高频率的频谱范围来提高信噪比或减小在有用的光谱范围内的量化噪声。

9. 发明授权

US06181215B2 Quartz oscillator circuit having synchronously switched frequency adjusting capacitors 失效
标题翻译：具有同步开关频率调节电容器的石英振荡器电路
公开(公告)号：US06181215B2
公开(公告)日：2001-01-30
申请号：US09519542
申请日：2000-03-06
申请人： Franz Kuttner
发明人： Franz Kuttner
IPC分类号： H03B536
CPC分类号： H03B5/366 , H03J2200/10 , H03K3/0307 , H03L7/0991
摘要： The oscillator circuit has a first and a second circuit node and a parallel circuit of a quartz resonator, a first inverter, and a first resistor element connected between the circuit nodes. The first circuit node is connected to a reference potential via a first capacitor circuit, and the second circuit node is connected to the reference potential via a second capacitor circuit. The first capacitor circuit has at least two capacitors whose first electrode is connected to the reference potential, and whose second electrode is connected to the first circuit node via one switching element each. Furthermore, the oscillator circuit has a precharging circuit for precharging the capacitors, and a synchronizing circuit for switching in the capacitors at an instant in which the precharging potential corresponds to the potential at the first circuit node.
摘要翻译：振荡器电路具有连接在电路节点之间的第一和第二电路节点和石英谐振器，第一反相器和第一电阻元件的并联电路。第一电路节点通过第一电容器电路连接到参考电位，并且第二电路节点经由第二电容器电路连接到参考电位。第一电容器电路具有至少两个电容器，其第一电极连接到参考电位，并且其第二电极通过一个开关元件连接到第一电路节点。此外，振荡器电路具有用于对电容器进行预充电的预充电电路，以及用于在预充电电位对应于第一电路节点处的电位的瞬间切换电容器的同步电路。

10. 发明授权

US5825316A Method for the self-calibration of an A/D or D/A converter in which the weighted references of the at least one main network are partially calibrated once per calibration cycle 失效
标题翻译：用于A / D或D / A转换器的自校准的方法，其中至少一个主网络的加权参考被校准一次校准一次
公开(公告)号：US5825316A
公开(公告)日：1998-10-20
申请号：US627968
申请日：1996-04-04
申请人： Franz Kuttner
发明人： Franz Kuttner
IPC分类号： H03M1/10 , H03M1/46 , H03M1/80
CPC分类号： H03M1/1052 , H03M1/468 , H03M1/804
摘要： A method for self-calibration of an analog/digital converter or of a digital/analog converter is performed in a converter including at least one main network with weighted reference elements and one correction network being coupled with the main network for error correction and having weighted further reference elements. The method includes self-calibrating a portion of the reference elements of the main network between two conversions and ascertaining a correction value associated with the portion of the reference elements.
摘要翻译：一种用于模拟/数字转换器或数/模转换器的自校准的方法在包括至少一个具有加权参考元件的主网络的转换器中执行，并且一个校正网络与主网络耦合用于纠错并具有加权其他参考资料。该方法包括在两个转换之间自主校准主网络的参考元件的一部分，并且确定与参考元件的该部分相关联的校正值。

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