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1. 发明授权

US06233191B1 Field programmable memory array 失效
标题翻译：现场可编程存储阵列
公开(公告)号：US06233191B1
公开(公告)日：2001-05-15
申请号：US09510326
申请日：2000-02-22
申请人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III
发明人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III
IPC分类号： G11C700
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

2. 发明授权

US5949719A Field programmable memory array 失效
公开(公告)号：US5949719A
公开(公告)日：1999-09-07
申请号：US190905
申请日：1998-11-12
申请人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
发明人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177 , G11C13/00
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

3. 发明授权

US5732246A Programmable array interconnect latch 失效
标题翻译：可编程阵列互连锁存器
公开(公告)号：US5732246A
公开(公告)日：1998-03-24
申请号：US480639
申请日：1995-06-07
申请人： Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Brian Allen Worth
发明人： Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Brian Allen Worth
IPC分类号： H03K19/173 , G01R31/3185 , H03K3/037 , H03K19/177 , G06F9/455 , G06F17/50
CPC分类号： G01R31/318519 , H03K19/17704 , H03K19/17748 , H03K3/0375
摘要： A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal. A secondary latch of the LSSD register is selectively coupled, per a third clock signal, to receive and latch therein latched data of the primary latch. Data representative of data latched within the secondary latch is provided at a secondary serial output, and selectively provided at the primary output node when enabled per a programmable enable signal. In yet a further embodiment, the LSSD register is part of a serial scan chain for selectively interfacing an interconnect boundary of the select block of the configured circuitry within the programmable gate array.
摘要翻译：可编程门阵列的给定互连包括可编程中继器电路，其实现对可编程门阵列内的配置电路的选择块的选择性隔离和测试。可编程中继器电路包括耦合到给定互连的第一部分的输入节点和耦合到给定互连的第二部分的输出节点。选择性缓冲电路有选择地将缓冲的输出信号输出到与输入节点处的逻辑状态相关的输出节点。信号存储电路也连接到输入节点，用于选择性地存储从输入节点接收的逻辑状态。在另一实施例中，信号存储电路包括LSSD寄存器。根据第二时钟信号，LSSD寄存器的主锁存器根据第一时钟信号，或者备选地从辅助串行输入节点选择性地从输入节点接收数据。每个第三时钟信号选择性地耦合LSSD寄存器的辅助锁存器，以在其中接收并锁存主锁存器的锁存数据。在辅助锁存器中锁存的数据的数据被提供在次级串行输出端，并且当每个可编程使能信号使能时，被选择地提供在主输出节点处。在又一个实施例中，LSSD寄存器是串行扫描链的一部分，用于选择性地接合可编程门阵列内的配置电路的选择块的互连边界。

4. 发明授权

US06373906B1 Method and apparatus for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed 有权
标题翻译：用于维特比检测广义部分响应信号的方法和装置，包括双向加法/比较/选择以提高通道速度
公开(公告)号：US06373906B1
公开(公告)日：2002-04-16
申请号：US09768802
申请日：2001-01-24
申请人： Roy Daron Cideciyan , Jonathan Darrel Coker , Evangelos S. Eleftheriou , Richard Leo Galbraith , Allen Prescott Haar , Frank Ray Keyser, III , David James Stanek
发明人： Roy Daron Cideciyan , Jonathan Darrel Coker , Evangelos S. Eleftheriou , Richard Leo Galbraith , Allen Prescott Haar , Frank Ray Keyser, III , David James Stanek
IPC分类号： H04L2706
CPC分类号： H04L1/0054 , H04L25/497
摘要： Apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value. The second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Zn of a partial matched filter or as outputs Wn of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow. The two-way compare for comparing first and second state metric input values can include a hard shift for providing an add for the first state metric input value and then a compare between a resultant first state metric input value and the second state metric input value.
摘要翻译：提供了用于实现用于维特比检测广义部分响应信号的高速和区域高效架构的装置，包括用于改善信道速度的双向加法/比较/选择。双向加法/比较/选择包括用于比较第一和第二状态度量输入值的双向比较以及用于分别添加第一和第二状态度量输入的双向比较并行的一对双向加法具有第二个输入值的值。第二输入值包括时变项或常数项。时变项表示为部分匹配滤波器的输出Zn或匹配滤波器的输出Wn。多路复用器耦合到一对双向加法器，多路复用器接收由双向比较控制的可选输入。耦合在一对双向加法器和多路复用器之间的一对移位器接收用于提供度量限制以避免下溢的移位控制输入。用于比较第一和第二状态度量输入值的双向比较可以包括用于为第一状态度量输入值提供加法，然后在得到的第一状态度量输入值与第二状态度量输入值之间进行比较的硬移位。

5. 发明授权

US6075745A Field programmable memory array 有权
标题翻译：现场可编程存储阵列
公开(公告)号：US6075745A
公开(公告)日：2000-06-13
申请号：US190628
申请日：1998-11-12
申请人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
发明人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

6. 发明授权

US6038192A Memory cells for field programmable memory array 有权
标题翻译：现场可编程存储器阵列的存储单元
公开(公告)号：US6038192A
公开(公告)日：2000-03-14
申请号：US189391
申请日：1998-11-10
申请人： Kim P. N. Clinton , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
发明人： Kim P. N. Clinton , Joseph Andrew Iadanza , Frank Ray Keyser, III , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

7. 发明授权

US6021513A Testable programmable gate array and associated LSSD/deterministic test methodology 失效
标题翻译：可测量可编程门阵列和相关的LSSD /确定性测试方法
公开(公告)号：US6021513A
公开(公告)日：2000-02-01
申请号：US181736
申请日：1998-10-28
申请人： Wayne Kevin Beebe , Sally Botala , Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Ronald Raymond Palmer , Brian Worth
发明人： Wayne Kevin Beebe , Sally Botala , Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Ronald Raymond Palmer , Brian Worth
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/82
CPC分类号： G01R31/318519 , G01R31/318558
摘要： A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.
摘要翻译：可编程门阵列包括用于测试可编程门阵列的各种功能子系统的测试子系统。采用测试子系统的一系列测试方法测试可编程门阵列的功能，考虑到各个子系统的相互依赖关系，从而使其中的故障隔离成为可能。

8. 发明授权

US5836007A Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles 失效
标题翻译：用于提高存储器组件尺寸和访问速度的方法和系统，包括分割位线和备用预充电/访问周期
公开(公告)号：US5836007A
公开(公告)日：1998-11-10
申请号：US528177
申请日：1995-09-14
申请人： Kim P. N. Clinton , Frank Ray Keyser III , Wendell Ray Larsen
发明人： Kim P. N. Clinton , Frank Ray Keyser III , Wendell Ray Larsen
IPC分类号： G11C11/41 , G11C7/10 , G11C7/12 , G11C7/18 , H01L27/112 , H03K19/177 , G11C7/00
CPC分类号： G11C7/18 , G11C7/1042 , G11C7/12 , H01L27/112
摘要： A memory system having split logical bit lines and interleaved pre-charge/access cycles is provided. A bit line access circuit supports multiple conductors per logical bit line and pre-charges the conductors before access cycles thereto. The access cycles for one logical bit line are performed simultaneous with the pre-charge cycles for another logical bit line by the access circuit. Virtual reading is provided for eliminated memory cells. The memory system can be used in a programmable gate array having memory cells distributed throughout for programming respective programmable resources.
摘要翻译：提供具有分离的逻辑位线和交错的预充电/访问周期的存储器系统。位线访问电路每个逻辑位线支持多个导体，并在导体访问周期之前对导体进行预充电。一个逻辑位线的访问周期与存取电路的另一个逻辑位线的预充电周期同时执行。为消除的存储单元提供虚拟阅读。存储器系统可用于具有分布在整个用于编程相应可编程资源的存储器单元的可编程门阵列中。

9. 发明授权

US5717346A Low skew multiplexer network and programmable array clock/reset application thereof 失效
标题翻译：低偏斜多路复用器网络及其可编程阵列时钟/复位应用
公开(公告)号：US5717346A
公开(公告)日：1998-02-10
申请号：US709074
申请日：1996-09-06
申请人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
发明人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
IPC分类号： G06F15/78 , G06F1/10 , H01L21/82 , H03K19/0175 , H03K19/173 , H03K19/177 , H03K19/00
CPC分类号： H03K19/1774 , H03K19/1737 , H03K19/17704
摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.
摘要翻译：公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。时钟门电路与每个逻辑单元中的输出多路复用器协同控制。网络被设计为具有最小化信号偏移的特征，包括作为信号传播距离的函数的信号源缓冲，多路复用器信号缓冲和输出驱动器尺寸。

10. 发明授权

US5703498A Programmable array clock/reset resource 失效
标题翻译：可编程阵列时钟/复位资源
公开(公告)号：US5703498A
公开(公告)日：1997-12-30
申请号：US709060
申请日：1996-09-06
申请人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
发明人： Scott Whitney Gould , Frederick Curtis Furtek , Frank Ray Keyser, III , Brian A. Worth , Terrance John Zittritsch
IPC分类号： G06F15/78 , G06F1/10 , H01L21/82 , H03K19/0175 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1774 , H03K19/1737 , H03K19/17704
摘要： A signal distribution architecture for clock and reset signal distribution in a programmable array is disclosed. The architecture includes separate networks for distributing clock and reset signals to logic cells of the array. Each network includes a plurality of column multiplexers for selecting a column clock or reset signal from a plurality of system clock or reset signals. Within each column of logic cells are positioned sector multiplexers for selecting a sector clock or reset signal from a plurality of column clock or reset signals. The clock and reset signals are applied to the combinatorial and sequential logic circuits of each logic cell associated with a given sector multiplexer. A clock gate circuit is controlled cooperatively with an output multiplexer in each logic cell. The networks are designed with features to minimize signal skew including signal source buffering, multiplexer signal buffering and output driver sizing as a function of signal propagation distance.
摘要翻译：公开了一种用于可编程阵列中的时钟和复位信号分配的信号分配架构。该架构包括用于将时钟和复位信号分配给阵列的逻辑单元的单独网络。每个网络包括多个列复用器，用于从多个系统时钟或复位信号中选择列时钟或复位信号。在逻辑单元的每列中，定位了用于从多个列时钟或复位信号中选择扇区时钟或复位信号的扇区多路复用器。时钟和复位信号被施加到与给定扇区多路复用器相关联的每个逻辑单元的组合和顺序逻辑电路。时钟门电路与每个逻辑单元中的输出多路复用器协同控制。网络被设计为具有最小化信号偏移的特征，包括作为信号传播距离的函数的信号源缓冲，多路复用器信号缓冲和输出驱动器尺寸。

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