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1. 发明授权

US5867507A Testable programmable gate array and associated LSSD/deterministic test methodology 失效
公开(公告)号：US5867507A
公开(公告)日：1999-02-02
申请号：US570846
申请日：1995-12-12
申请人： Wayne Kevin Beebe , Sally Botala , Scott Whitney Gould , Frank Ray Keyser III , Wendell Ray Larsen , Ronald Raymond Palmer , Brian Worth
发明人： Wayne Kevin Beebe , Sally Botala , Scott Whitney Gould , Frank Ray Keyser III , Wendell Ray Larsen , Ronald Raymond Palmer , Brian Worth
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/82
CPC分类号： G01R31/318519 , G01R31/318558
摘要： A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.

2. 发明授权

US6021513A Testable programmable gate array and associated LSSD/deterministic test methodology 失效
标题翻译：可测量可编程门阵列和相关的LSSD /确定性测试方法
公开(公告)号：US6021513A
公开(公告)日：2000-02-01
申请号：US181736
申请日：1998-10-28
申请人： Wayne Kevin Beebe , Sally Botala , Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Ronald Raymond Palmer , Brian Worth
发明人： Wayne Kevin Beebe , Sally Botala , Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Ronald Raymond Palmer , Brian Worth
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3185 , G06F11/22 , H01L21/82
CPC分类号： G01R31/318519 , G01R31/318558
摘要： A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.
摘要翻译：可编程门阵列包括用于测试可编程门阵列的各种功能子系统的测试子系统。采用测试子系统的一系列测试方法测试可编程门阵列的功能，考虑到各个子系统的相互依赖关系，从而使其中的故障隔离成为可能。

3. 发明授权

US5732246A Programmable array interconnect latch 失效
标题翻译：可编程阵列互连锁存器
公开(公告)号：US5732246A
公开(公告)日：1998-03-24
申请号：US480639
申请日：1995-06-07
申请人： Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Brian Allen Worth
发明人： Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Brian Allen Worth
IPC分类号： H03K19/173 , G01R31/3185 , H03K3/037 , H03K19/177 , G06F9/455 , G06F17/50
CPC分类号： G01R31/318519 , H03K19/17704 , H03K19/17748 , H03K3/0375
摘要： A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal. A secondary latch of the LSSD register is selectively coupled, per a third clock signal, to receive and latch therein latched data of the primary latch. Data representative of data latched within the secondary latch is provided at a secondary serial output, and selectively provided at the primary output node when enabled per a programmable enable signal. In yet a further embodiment, the LSSD register is part of a serial scan chain for selectively interfacing an interconnect boundary of the select block of the configured circuitry within the programmable gate array.
摘要翻译：可编程门阵列的给定互连包括可编程中继器电路，其实现对可编程门阵列内的配置电路的选择块的选择性隔离和测试。可编程中继器电路包括耦合到给定互连的第一部分的输入节点和耦合到给定互连的第二部分的输出节点。选择性缓冲电路有选择地将缓冲的输出信号输出到与输入节点处的逻辑状态相关的输出节点。信号存储电路也连接到输入节点，用于选择性地存储从输入节点接收的逻辑状态。在另一实施例中，信号存储电路包括LSSD寄存器。根据第二时钟信号，LSSD寄存器的主锁存器根据第一时钟信号，或者备选地从辅助串行输入节点选择性地从输入节点接收数据。每个第三时钟信号选择性地耦合LSSD寄存器的辅助锁存器，以在其中接收并锁存主锁存器的锁存数据。在辅助锁存器中锁存的数据的数据被提供在次级串行输出端，并且当每个可编程使能信号使能时，被选择地提供在主输出节点处。在又一个实施例中，LSSD寄存器是串行扫描链的一部分，用于选择性地接合可编程门阵列内的配置电路的选择块的互连边界。

4. 发明授权

US5836007A Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles 失效
标题翻译：用于提高存储器组件尺寸和访问速度的方法和系统，包括分割位线和备用预充电/访问周期
公开(公告)号：US5836007A
公开(公告)日：1998-11-10
申请号：US528177
申请日：1995-09-14
申请人： Kim P. N. Clinton , Frank Ray Keyser III , Wendell Ray Larsen
发明人： Kim P. N. Clinton , Frank Ray Keyser III , Wendell Ray Larsen
IPC分类号： G11C11/41 , G11C7/10 , G11C7/12 , G11C7/18 , H01L27/112 , H03K19/177 , G11C7/00
CPC分类号： G11C7/18 , G11C7/1042 , G11C7/12 , H01L27/112
摘要： A memory system having split logical bit lines and interleaved pre-charge/access cycles is provided. A bit line access circuit supports multiple conductors per logical bit line and pre-charges the conductors before access cycles thereto. The access cycles for one logical bit line are performed simultaneous with the pre-charge cycles for another logical bit line by the access circuit. Virtual reading is provided for eliminated memory cells. The memory system can be used in a programmable gate array having memory cells distributed throughout for programming respective programmable resources.
摘要翻译：提供具有分离的逻辑位线和交错的预充电/访问周期的存储器系统。位线访问电路每个逻辑位线支持多个导体，并在导体访问周期之前对导体进行预充电。一个逻辑位线的访问周期与存取电路的另一个逻辑位线的预充电周期同时执行。为消除的存储单元提供虚拟阅读。存储器系统可用于具有分布在整个用于编程相应可编程资源的存储器单元的可编程门阵列中。

5. 发明授权

US5692147A Memory mapping method and apparatus to fold sparsely populated structures into densely populated memory columns or rows by selectively transposing X and Y address portions, and programmable gate array applications thereof 失效
标题翻译：存储器映射方法和装置，用于通过选择性地转置X和Y地址部分将稀疏人口化的结构折叠成密集的存储器列或行，以及可编程门阵列应用
公开(公告)号：US5692147A
公开(公告)日：1997-11-25
申请号：US488314
申请日：1995-06-07
申请人： Wendell Ray Larsen , Frank Ray Keyser , Brian A. Worth
发明人： Wendell Ray Larsen , Frank Ray Keyser , Brian A. Worth
IPC分类号： H01L21/82 , H01L21/8247 , H01L27/115 , H03K19/177 , G06F12/06
CPC分类号： H03K19/17736 , H03K19/17704
摘要： A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field programmable gate array. A controller addresses the memory device with an N-bit address for retrieving given configuration data. An address decoder and sequencer divides the N-bit address into first, second, and third portions and employs the first and third portions interchangeably, in accordance with the second portion, for addressing respective x and y dimensions of the plurality of programmable resources for selecting an associated programmable resource to be configured in accordance with the retrieved configuration data.
摘要翻译：现场可编程门阵列具有可针对x，y二维阵列的每个x和y维度寻址的多个可编程资源。存储器装置提供存储用于配置现场可编程门阵列的相关可编程资源的配置数据的多个存储器单元。控制器利用N位地址寻址存储器设备，以检索给定的配置数据。地址解码器和定序器将N位地址划分为第一，第二和第三部分，并且根据第二部分可互换地采用第一和第三部分，用于寻址用于选择的多个可编程资源的各自的x和y维度根据检索到的配置数据来配置的相关联的可编程资源。

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