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1. 发明授权

US06373906B1 Method and apparatus for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed 有权
标题翻译：用于维特比检测广义部分响应信号的方法和装置，包括双向加法/比较/选择以提高通道速度
公开(公告)号：US06373906B1
公开(公告)日：2002-04-16
申请号：US09768802
申请日：2001-01-24
申请人： Roy Daron Cideciyan , Jonathan Darrel Coker , Evangelos S. Eleftheriou , Richard Leo Galbraith , Allen Prescott Haar , Frank Ray Keyser, III , David James Stanek
发明人： Roy Daron Cideciyan , Jonathan Darrel Coker , Evangelos S. Eleftheriou , Richard Leo Galbraith , Allen Prescott Haar , Frank Ray Keyser, III , David James Stanek
IPC分类号： H04L2706
CPC分类号： H04L1/0054 , H04L25/497
摘要： Apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value. The second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Zn of a partial matched filter or as outputs Wn of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow. The two-way compare for comparing first and second state metric input values can include a hard shift for providing an add for the first state metric input value and then a compare between a resultant first state metric input value and the second state metric input value.
摘要翻译：提供了用于实现用于维特比检测广义部分响应信号的高速和区域高效架构的装置，包括用于改善信道速度的双向加法/比较/选择。双向加法/比较/选择包括用于比较第一和第二状态度量输入值的双向比较以及用于分别添加第一和第二状态度量输入的双向比较并行的一对双向加法具有第二个输入值的值。第二输入值包括时变项或常数项。时变项表示为部分匹配滤波器的输出Zn或匹配滤波器的输出Wn。多路复用器耦合到一对双向加法器，多路复用器接收由双向比较控制的可选输入。耦合在一对双向加法器和多路复用器之间的一对移位器接收用于提供度量限制以避免下溢的移位控制输入。用于比较第一和第二状态度量输入值的双向比较可以包括用于为第一状态度量输入值提供加法，然后在得到的第一状态度量输入值与第二状态度量输入值之间进行比较的硬移位。

2. 发明授权

US6118707A Method of operating a field programmable memory array with a field programmable gate array 有权
标题翻译：用现场可编程门阵列操作现场可编程存储器阵列的方法
公开(公告)号：US6118707A
公开(公告)日：2000-09-12
申请号：US189750
申请日：1998-11-10
申请人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Terrance John Zittritsch
发明人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供了具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

3. 发明授权

US5734582A Method and system for layout and schematic generation for heterogeneous arrays 失效
公开(公告)号：US5734582A
公开(公告)日：1998-03-31
申请号：US570850
申请日：1995-12-12
申请人： Allan Robert Bertolet , Kim P. N. Clinton , Scott Whitney Gould , Frank Ray Keyser, III , Timothy Shawn Reny , Terrance John Zittritsch
发明人： Allan Robert Bertolet , Kim P. N. Clinton , Scott Whitney Gould , Frank Ray Keyser, III , Timothy Shawn Reny , Terrance John Zittritsch
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.

4. 发明授权

US6130854A Programmable address decoder for field programmable memory array 有权
标题翻译：用于现场可编程存储器阵列的可编程地址解码器
公开(公告)号：US6130854A
公开(公告)日：2000-10-10
申请号：US190871
申请日：1998-11-12
申请人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Terrance John Zittritsch
发明人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

5. 发明授权

US5745734A Method and system for programming a gate array using a compressed configuration bit stream 失效
标题翻译：使用压缩配置位流对门阵列进行编程的方法和系统
公开(公告)号：US5745734A
公开(公告)日：1998-04-28
申请号：US536901
申请日：1995-09-29
申请人： David John Craft , Scott Whitney Gould , Frank Ray Keyser, III , Brian Worth
发明人： David John Craft , Scott Whitney Gould , Frank Ray Keyser, III , Brian Worth
IPC分类号： H03K19/173 , G06T9/00 , H03K19/177 , H03M7/30 , H03M7/40 , H03M7/46
CPC分类号： G06T9/005 , H03M7/3084
摘要： A generalized data decompression engine is incorporated within a field programmable gate array ("FPGA"). The generalized data decompression engine uses a general purpose data decompression technique such as, for example, a Lempel-Ziv type technique. During operation, a compressed configuration bit stream is received by the generalized data decompression engine in the FPGA and is decompressed thereby. A resultant decompressed configuration bit stream is then used to program logic cells within the FPGA.
摘要翻译：通用数据解压缩引擎并入现场可编程门阵列（“FPGA”）中。广义数据解压缩引擎使用通用数据解压缩技术，例如Lempel-Ziv型技术。在操作期间，压缩配置位流由FPGA中的通用数据解压缩引擎接收，并由此解压缩。然后使用结果解压缩的配置位流来对FPGA内的逻辑单元进行编程。

6. 发明授权

US06233191B1 Field programmable memory array 失效
标题翻译：现场可编程存储阵列
公开(公告)号：US06233191B1
公开(公告)日：2001-05-15
申请号：US09510326
申请日：2000-02-22
申请人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III
发明人： Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III
IPC分类号： G11C700
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

7. 发明授权

US5949719A Field programmable memory array 失效
公开(公告)号：US5949719A
公开(公告)日：1999-09-07
申请号：US190905
申请日：1998-11-12
申请人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
发明人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177 , G11C13/00
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

8. 发明授权

US5732246A Programmable array interconnect latch 失效
标题翻译：可编程阵列互连锁存器
公开(公告)号：US5732246A
公开(公告)日：1998-03-24
申请号：US480639
申请日：1995-06-07
申请人： Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Brian Allen Worth
发明人： Scott Whitney Gould , Frank Ray Keyser, III , Wendell Ray Larsen , Brian Allen Worth
IPC分类号： H03K19/173 , G01R31/3185 , H03K3/037 , H03K19/177 , G06F9/455 , G06F17/50
CPC分类号： G01R31/318519 , H03K19/17704 , H03K19/17748 , H03K3/0375
摘要： A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal. A secondary latch of the LSSD register is selectively coupled, per a third clock signal, to receive and latch therein latched data of the primary latch. Data representative of data latched within the secondary latch is provided at a secondary serial output, and selectively provided at the primary output node when enabled per a programmable enable signal. In yet a further embodiment, the LSSD register is part of a serial scan chain for selectively interfacing an interconnect boundary of the select block of the configured circuitry within the programmable gate array.
摘要翻译：可编程门阵列的给定互连包括可编程中继器电路，其实现对可编程门阵列内的配置电路的选择块的选择性隔离和测试。可编程中继器电路包括耦合到给定互连的第一部分的输入节点和耦合到给定互连的第二部分的输出节点。选择性缓冲电路有选择地将缓冲的输出信号输出到与输入节点处的逻辑状态相关的输出节点。信号存储电路也连接到输入节点，用于选择性地存储从输入节点接收的逻辑状态。在另一实施例中，信号存储电路包括LSSD寄存器。根据第二时钟信号，LSSD寄存器的主锁存器根据第一时钟信号，或者备选地从辅助串行输入节点选择性地从输入节点接收数据。每个第三时钟信号选择性地耦合LSSD寄存器的辅助锁存器，以在其中接收并锁存主锁存器的锁存数据。在辅助锁存器中锁存的数据的数据被提供在次级串行输出端，并且当每个可编程使能信号使能时，被选择地提供在主输出节点处。在又一个实施例中，LSSD寄存器是串行扫描链的一部分，用于选择性地接合可编程门阵列内的配置电路的选择块的互连边界。

9. 发明授权

US6044031A Programmable bit line drive modes for memory arrays 有权
标题翻译：存储阵列的可编程位线驱动模式
公开(公告)号：US6044031A
公开(公告)日：2000-03-28
申请号：US190919
申请日：1998-11-12
申请人： Joseph Andrew Iadanza , Frank Ray Keyser, III
发明人： Joseph Andrew Iadanza , Frank Ray Keyser, III
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177 , G11C7/04
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

10. 发明授权

US6023421A Selective connectivity between memory sub-arrays and a hierarchical bit line structure in a memory array 失效
标题翻译：存储器子阵列与存储器阵列中的分层位线结构之间的选择性连接
公开(公告)号：US6023421A
公开(公告)日：2000-02-08
申请号：US190920
申请日：1998-11-12
申请人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
发明人： Kim P. N. Clinton , Scott Whitney Gould , Joseph Andrew Iadanza , Frank Ray Keyser, III , Ralph David Kilmoyer , Michael Joseph Laramie , Victor Paul Seidel , Terrance John Zittritsch
IPC分类号： G06F5/10 , G06F7/78 , G11C5/00 , G11C7/00 , G11C7/10 , G11C7/12 , G11C8/00 , H03K19/177 , G11C5/06
CPC分类号： G06F7/785 , G06F5/10 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C8/00 , H03K19/17704 , H03K19/1776
摘要： A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
摘要翻译：提供了具有多个子阵列的现场可编程存储器阵列。提供可编程地址解码器，可编程分层位线布置，可编程I / O布置等功能，以使阵列的部分能够编程成选定的模式。这些模式可以包括宽存储器，深存储器，FIFO，LIFO等。公开了本发明的实施例，其中现场可编程存储器阵列与现场可编程门阵列的可编程资源集成。

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