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1. 发明授权

US07488611B2 Devices and methods for integrated circuit manufacturing 有权
标题翻译：集成电路制造的设备和方法
公开(公告)号：US07488611B2
公开(公告)日：2009-02-10
申请号：US11294822
申请日：2005-12-06
申请人： Simon Dodd , Frank Randolph Bryant , Paul I. Mikulan
发明人： Simon Dodd , Frank Randolph Bryant , Paul I. Mikulan
IPC分类号： H01L21/00
CPC分类号： B41J2/14129 , B41J2/14072 , B41J2/1603 , B41J2/1629 , B41J2/1631
摘要： Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.
摘要翻译：提供了集成电路及其制造方法。特别地，提供了具有屏蔽元件的集成电路。

2. 发明授权

US06780718B2 Transistor structure and method for making same 失效
标题翻译：晶体管结构及其制作方法
公开(公告)号：US06780718B2
公开(公告)日：2004-08-24
申请号：US08159461
申请日：1993-11-30
申请人： Frank Randolph Bryant
发明人： Frank Randolph Bryant
IPC分类号： H01L2100
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.
摘要翻译：晶体管中的栅极结构及其制造方法。在基板上形成栅极结构。栅极结构包括三层：氧化物层，氮化物层和多晶硅层。氧化物层位于衬底上，氮化物层位于氧化物层上，多晶硅层位于氮化物层上。栅极结构被再氧化以在栅极结构上形成一层氧化物。

3. 发明授权

US06472246B1 Electrostatic discharge protection for integrated circuit sensor passivation 有权
标题翻译：集成电路传感器钝化的静电放电保护
公开(公告)号：US06472246B1
公开(公告)日：2002-10-29
申请号：US09473365
申请日：1999-12-28
申请人： Danielle A. Thomas , Frank Randolph Bryant
发明人： Danielle A. Thomas , Frank Randolph Bryant
IPC分类号： H01L2100
CPC分类号： G06K9/00053 , Y10S438/931 , Y10S438/953 , Y10S438/958
摘要： A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.
摘要翻译：一种用于产生集成电路钝化（24）的结构和方法，包括：电路（16），电介质（18）和金属板（20），绝缘层（26）设置在绝缘层（26）上，电绝缘隔离电路（16），以及放电层（32），其被沉积以形成保护电路（16）免受例如手指引起的静电放电的钝化（24）。

4. 发明授权

US5751064A Intermediate structure for integrated circuit devices 失效
标题翻译：集成电路器件的中间结构
公开(公告)号：US5751064A
公开(公告)日：1998-05-12
申请号：US398110
申请日：1995-03-03
申请人： Frank Randolph Bryant , Loi Ngoc Nguyen
发明人： Frank Randolph Bryant , Loi Ngoc Nguyen
IPC分类号： H01L21/28 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76877 , H01L21/7684
摘要： A structure useful during the fabrication of semiconductor integrated circuits. At least one layer is formed over an insulating layer, and an opening formed to an underlying substrate. A conductive layer is formed over the at least one layer, which simultaneously forms a conductive plug in the bottom of the opening. An insulating layer plug is formed over the conductive plug to provide protection while the conductive layer on the at least one layer is removed.
摘要翻译：在半导体集成电路制造期间有用的结构。在绝缘层上形成至少一层，和形成在下面的基底上的开口。导电层形成在至少一个层上，其同时在开口的底部形成导电插塞。绝缘层插塞形成在导电插头上方以提供保护，同时去除至少一层上的导电层。

5. 发明授权

US5742095A Method of fabricating planar regions in an integrated circuit 失效
标题翻译：在集成电路中制造平面区域的方法
公开(公告)号：US5742095A
公开(公告)日：1998-04-21
申请号：US752749
申请日：1996-11-20
申请人： Frank Randolph Bryant , Robert Louis Hodges
发明人： Frank Randolph Bryant , Robert Louis Hodges
IPC分类号： H01L21/76 , H01L21/28 , H01L21/314 , H01L21/32 , H01L21/762 , H01L21/768 , H01L23/522 , H01L29/51 , H01L29/78 , H01L23/58
CPC分类号： H01L21/28176 , H01L21/28202 , H01L21/3145 , H01L21/32 , H01L21/76216 , H01L29/513 , H01L29/518
摘要： A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect. A silicide or other conductive layer, such as a second polysilicon layer, may be formed over the remaining first polysilicon regions and a portion of the field oxide layer to connect the gate and interconnect since the upper surface of the first polysilicon layer is substantially planar with the upper surface of the field oxide region and does not cross over the field oxide region.
摘要翻译：提供一种用于形成半导体集成电路的平面的方法和根据该集成电路形成的集成电路。在硅衬底上形成栅氧化层。在栅极氧化物层上形成第一多晶硅层，在第一多晶硅层上形成氮化物层。然后对第一多晶硅和氮化物层进行构图和蚀刻，以形成露出栅极氧化物层的一部分的开口。然后进行氧化步骤以在开口中形成场氧化物区域。场氧化物区域形成为具有与第一多晶硅层的上表面大致平坦的上表面的厚度。然后去除氮化物层，并对栅极氧化物和第一多晶硅层进行图案化和蚀刻以形成栅电极和互连。可以在剩余的第一多晶硅区域和场氧化物层的一部分上形成硅化物或其它导电层，例如第二多晶硅层，以连接栅极和互连，因为第一多晶硅层的上表面基本上是平面的，场氧化物区域的上表面并且不与场氧化物区域交叉。

6. 发明授权

US07704841B2 Transistor structure and method for making same 失效
标题翻译：晶体管结构及其制作方法
公开(公告)号：US07704841B2
公开(公告)日：2010-04-27
申请号：US12290607
申请日：2008-10-31
申请人： Frank Randolph Bryant
发明人： Frank Randolph Bryant
IPC分类号： H01L21/00
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.
摘要翻译：公开了一种晶体管中的栅极结构及其制造方法。在基板上形成栅极结构。栅极结构包括三层：氧化物层，氮化物层和多晶硅层。氧化物层位于衬底上，氮化物层位于氧化物层上，多晶硅层位于氮化物层上。栅极结构被再氧化以在栅极结构上形成一层氧化物。

7. 发明授权

US07004558B2 Fluid ejection device including integrated circuit with shielding element 有权
标题翻译：流体喷射装置包括具有屏蔽元件的集成电路
公开(公告)号：US07004558B2
公开(公告)日：2006-02-28
申请号：US10280414
申请日：2002-10-25
申请人： Simon Dodd , Frank Randolph Bryant , Paul I. Mikulan
发明人： Simon Dodd , Frank Randolph Bryant , Paul I. Mikulan
IPC分类号： B41J2/165
CPC分类号： B41J2/14072 , B41J2/14129 , B41J2202/13
摘要： Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.
摘要翻译：提供了集成电路及其制造方法。特别地，提供了具有屏蔽元件的集成电路。

8. 发明授权

US06188056B1 Solid state optical imaging pixel with resistive load 失效
标题翻译：具有电阻负载的固态光学成像像素
公开(公告)号：US06188056B1
公开(公告)日：2001-02-13
申请号：US09103753
申请日：1998-06-24
申请人： Alexander Kalnitsky , Frank Randolph Bryant , Marco Sabatini
发明人： Alexander Kalnitsky , Frank Randolph Bryant , Marco Sabatini
IPC分类号： H01L2700
CPC分类号： H01L27/14665 , H01L27/14609 , H01L31/0352
摘要： Disclosed is a CMOS image sensor that includes pixels employing a radiation-sensitive resistive element in which the resistance of the element changes in response to the quantity of radiation striking it. The resistive elements are made from an appropriately doped polycrystalline semiconductor material such as polysilicon. The pixels are provided on a semiconductor device in which the photosensitive resistive elements are provided on a first layer and the pixel associated transistors are provided on a second layer. The fill factor may be approach 100 percent for such pixels.
摘要翻译：公开了一种CMOS图像传感器，其包括采用辐射敏感电阻元件的像素，其中元件的电阻响应于其的辐射量而变化。电阻元件由诸如多晶硅的适当掺杂的多晶半导体材料制成。像素设置在半导体器件上，其中光敏电阻元件设置在第一层上，像素相关联的晶体管设置在第二层上。这种像素的填充因子可能接近100％。

9. 发明授权

US6140684A SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers 失效
标题翻译：具有介电侧壁间隔物的SRAM单元结构和沿着侧壁间隔物限定的漏极和沟道区域
公开(公告)号：US6140684A
公开(公告)日：2000-10-31
申请号：US881342
申请日：1997-06-24
申请人： Tsiu Chiu Chan , Frank Randolph Bryant
发明人： Tsiu Chiu Chan , Frank Randolph Bryant
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/116
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.
摘要翻译：具有薄膜上拉晶体管的六晶体管静态随机存取存储器（SRAM）单元及其制造方法包括提供两个第一导电类型的体硅下拉晶体管，两个主动门控上拉薄膜晶体管（TFT），第二导电类型，双通道，公共字线和两个位线触点。大量硅下拉晶体管，两个有源选通上拉TFT和两个通过门连接在四个共享触点。此外，两个体硅下拉晶体管和两个主动选通上拉TFT形成有两个多晶硅层，多晶硅层（poly1）中的第一个被浸渍，并且包括用于两个体硅片的多晶硅栅电极，下降晶体管。多晶硅层（poly2）中的第二个包括沿着多晶硅栅电极的侧边缘设置的期望的poly2桁条，形成上拉TFT的相应沟道区域的期望的poly2桁条。

10. 发明授权

US5874769A Mosfet isolation structure with planar surface 失效
标题翻译：具有平面表面的Mosfet隔离结构
公开(公告)号：US5874769A
公开(公告)日：1999-02-23
申请号：US182809
申请日：1994-01-14
申请人： Tsiu Chiu Chan , Frank Randolph Bryant
发明人： Tsiu Chiu Chan , Frank Randolph Bryant
IPC分类号： H01L21/76 , H01L21/28 , H01L21/3105 , H01L21/32 , H01L21/762 , H01L29/423 , H01L29/49 , H01L29/78 , H01L23/58
CPC分类号： H01L29/4933 , H01L21/28123 , H01L21/31055 , H01L21/32 , H01L21/76202 , H01L29/42376 , H01L2924/0002
摘要： A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.
摘要翻译：提供了一种用于半导体集成电路的平面的方法和根据该集成电路形成的集成电路。在衬底上形成导电层。在导电层上形成氮化硅层。然后在氮化硅层上形成并图案化光致抗蚀剂层。蚀刻氮化硅层和导电层以形成露出衬底的一部分的开口。然后除去光致抗蚀剂层。暴露的基板和沿开口侧壁暴露的导电层的一部分被氧化。在氮化硅层和开口中形成平面化绝缘层，例如旋涂玻璃。将绝缘层回蚀刻以露出氮化硅，其中绝缘层的上表面与导电层的上表面平齐。然后去除氮化硅层。然后在导电层上形成平面硅化物层。

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