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1. 发明授权

US06472246B1 Electrostatic discharge protection for integrated circuit sensor passivation 有权
标题翻译：集成电路传感器钝化的静电放电保护
公开(公告)号：US06472246B1
公开(公告)日：2002-10-29
申请号：US09473365
申请日：1999-12-28
申请人： Danielle A. Thomas , Frank Randolph Bryant
发明人： Danielle A. Thomas , Frank Randolph Bryant
IPC分类号： H01L2100
CPC分类号： G06K9/00053 , Y10S438/931 , Y10S438/953 , Y10S438/958
摘要： A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.
摘要翻译：一种用于产生集成电路钝化（24）的结构和方法，包括：电路（16），电介质（18）和金属板（20），绝缘层（26）设置在绝缘层（26）上，电绝缘隔离电路（16），以及放电层（32），其被沉积以形成保护电路（16）免受例如手指引起的静电放电的钝化（24）。

2. 发明授权

US6091082A Electrostatic discharge protection for integrated circuit sensor passivation 失效
公开(公告)号：US6091082A
公开(公告)日：2000-07-18
申请号：US024094
申请日：1998-02-17
申请人： Danielle A. Thomas , Frank Randolph Bryant
发明人： Danielle A. Thomas , Frank Randolph Bryant
IPC分类号： G06K9/00
CPC分类号： G06K9/00053 , Y10S438/931 , Y10S438/953 , Y10S438/958
摘要： A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.

3. 发明授权

US07488611B2 Devices and methods for integrated circuit manufacturing 有权
标题翻译：集成电路制造的设备和方法
公开(公告)号：US07488611B2
公开(公告)日：2009-02-10
申请号：US11294822
申请日：2005-12-06
申请人： Simon Dodd , Frank Randolph Bryant , Paul I. Mikulan
发明人： Simon Dodd , Frank Randolph Bryant , Paul I. Mikulan
IPC分类号： H01L21/00
CPC分类号： B41J2/14129 , B41J2/14072 , B41J2/1603 , B41J2/1629 , B41J2/1631
摘要： Integrated circuits and methods for producing them are provided. In particular, integrated circuits with shielding elements are provided.
摘要翻译：提供了集成电路及其制造方法。特别地，提供了具有屏蔽元件的集成电路。

4. 发明授权

US06780718B2 Transistor structure and method for making same 失效
标题翻译：晶体管结构及其制作方法
公开(公告)号：US06780718B2
公开(公告)日：2004-08-24
申请号：US08159461
申请日：1993-11-30
申请人： Frank Randolph Bryant
发明人： Frank Randolph Bryant
IPC分类号： H01L2100
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.
摘要翻译：晶体管中的栅极结构及其制造方法。在基板上形成栅极结构。栅极结构包括三层：氧化物层，氮化物层和多晶硅层。氧化物层位于衬底上，氮化物层位于氧化物层上，多晶硅层位于氮化物层上。栅极结构被再氧化以在栅极结构上形成一层氧化物。

5. 发明授权

US5751064A Intermediate structure for integrated circuit devices 失效
标题翻译：集成电路器件的中间结构
公开(公告)号：US5751064A
公开(公告)日：1998-05-12
申请号：US398110
申请日：1995-03-03
申请人： Frank Randolph Bryant , Loi Ngoc Nguyen
发明人： Frank Randolph Bryant , Loi Ngoc Nguyen
IPC分类号： H01L21/28 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76877 , H01L21/7684
摘要： A structure useful during the fabrication of semiconductor integrated circuits. At least one layer is formed over an insulating layer, and an opening formed to an underlying substrate. A conductive layer is formed over the at least one layer, which simultaneously forms a conductive plug in the bottom of the opening. An insulating layer plug is formed over the conductive plug to provide protection while the conductive layer on the at least one layer is removed.
摘要翻译：在半导体集成电路制造期间有用的结构。在绝缘层上形成至少一层，和形成在下面的基底上的开口。导电层形成在至少一个层上，其同时在开口的底部形成导电插塞。绝缘层插塞形成在导电插头上方以提供保护，同时去除至少一层上的导电层。

6. 发明授权

US5742095A Method of fabricating planar regions in an integrated circuit 失效
标题翻译：在集成电路中制造平面区域的方法
公开(公告)号：US5742095A
公开(公告)日：1998-04-21
申请号：US752749
申请日：1996-11-20
申请人： Frank Randolph Bryant , Robert Louis Hodges
发明人： Frank Randolph Bryant , Robert Louis Hodges
IPC分类号： H01L21/76 , H01L21/28 , H01L21/314 , H01L21/32 , H01L21/762 , H01L21/768 , H01L23/522 , H01L29/51 , H01L29/78 , H01L23/58
CPC分类号： H01L21/28176 , H01L21/28202 , H01L21/3145 , H01L21/32 , H01L21/76216 , H01L29/513 , H01L29/518
摘要： A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect. A silicide or other conductive layer, such as a second polysilicon layer, may be formed over the remaining first polysilicon regions and a portion of the field oxide layer to connect the gate and interconnect since the upper surface of the first polysilicon layer is substantially planar with the upper surface of the field oxide region and does not cross over the field oxide region.
摘要翻译：提供一种用于形成半导体集成电路的平面的方法和根据该集成电路形成的集成电路。在硅衬底上形成栅氧化层。在栅极氧化物层上形成第一多晶硅层，在第一多晶硅层上形成氮化物层。然后对第一多晶硅和氮化物层进行构图和蚀刻，以形成露出栅极氧化物层的一部分的开口。然后进行氧化步骤以在开口中形成场氧化物区域。场氧化物区域形成为具有与第一多晶硅层的上表面大致平坦的上表面的厚度。然后去除氮化物层，并对栅极氧化物和第一多晶硅层进行图案化和蚀刻以形成栅电极和互连。可以在剩余的第一多晶硅区域和场氧化物层的一部分上形成硅化物或其它导电层，例如第二多晶硅层，以连接栅极和互连，因为第一多晶硅层的上表面基本上是平面的，场氧化物区域的上表面并且不与场氧化物区域交叉。

7. 发明申请

US20090124055A1 Transistor structure and method for making same 失效
标题翻译：晶体管结构及其制作方法
公开(公告)号：US20090124055A1
公开(公告)日：2009-05-14
申请号：US12290607
申请日：2008-10-31
申请人： Frank Randolph Bryant
发明人： Frank Randolph Bryant
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8234 , H01L21/302
CPC分类号： H01L21/28185 , H01L21/28176 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A gate structure in a transistor and method for fabricating the structure are disclosed. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.
摘要翻译：公开了一种晶体管中的栅极结构及其制造方法。在基板上形成栅极结构。栅极结构包括三层：氧化物层，氮化物层和多晶硅层。氧化物层位于衬底上，氮化物层位于氧化物层上，多晶硅层位于氮化物层上。栅极结构被再氧化以在栅极结构上形成一层氧化物。

8. 再颁专利

USRE40579E1 Structure for transistor devices in an SRAM cell 有权
标题翻译： SRAM单元中晶体管器件的结构
公开(公告)号：USRE40579E1
公开(公告)日：2008-11-25
申请号：US09694051
申请日：2000-10-20
申请人： Frank Randolph Bryant , Tsiu Chiu Chan
发明人： Frank Randolph Bryant , Tsiu Chiu Chan
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
摘要： An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.
摘要翻译：一种具有第一和第二传输门晶体管的SRAM存储单元。第一传输门晶体管包括连接到位线的第一源极/漏极，第二传输门晶体管具有连接到补码位线的第一源极/漏极。每个传输门晶体管具有连接到字线的栅极。 SRAM存储单元还包括被配置为存储锁存器的第一和第二下拉晶体管。第一下拉晶体管具有连接到所述第一传输栅极晶体管的第二源极/漏极的第一源极/漏极; 所述第二下拉晶体管具有连接到所述第二传输栅极晶体管的第二源极/漏极的第一源极/漏极。第一和第二下拉晶体管都具有连接到电源电压节点的第二源极/漏极。第一和第二传输门晶体管各自包括具有第一厚度的栅极氧化物层，并且第一和第二下拉晶体管各自包括具有第二厚度的栅极氧化物层，其中第一厚度不同于第二厚度。

9. 发明授权

US5972776A Method of forming a planar isolation structure in an integrated circuit 失效
标题翻译：在集成电路中形成平面隔离结构的方法
公开(公告)号：US5972776A
公开(公告)日：1999-10-26
申请号：US576955
申请日：1995-12-22
申请人： Frank Randolph Bryant
发明人： Frank Randolph Bryant
IPC分类号： H01L21/762
CPC分类号： H01L21/76205 , H01L21/76216
摘要： A method is provided for forming isolated regions of oxide of an integrate circuit, and an integrated circuit formed according to the same. A plurality of active areas is formed in an upper surface of a portion of a substrate body. A field oxide region is formed which separates at least two of the plurality of the active areas, wherein an upper surface of the field oxide region is substantially planar with an upper surface of the substrate body. Nitride spots are formed in the bulk of the field oxide region and not in the active area which do not need to be removed since they do not effect device integrity.
摘要翻译：提供一种用于形成集成电路的隔离氧化物区域的方法和根据该集成电路形成的集成电路。在基体的一部分的上表面上形成有多个有源区。形成场氧化物区域，其分离多个有源区域中的至少两个，其中场氧化物区域的上表面与衬底主体的上表面基本上是平面的。氮化物斑点形成在场氧化物区域的大部分中，而不是在不需要去除的有源区域中，因为它们不影响器件完整性。

10. 发明授权

US5729036A Integrated circuit transistor having drain junction offset 失效
标题翻译：具有漏极结偏移的集成电路晶体管
公开(公告)号：US5729036A
公开(公告)日：1998-03-17
申请号：US523366
申请日：1995-09-05
申请人： Frank Randolph Bryant , Robert Louis Hodges
发明人： Frank Randolph Bryant , Robert Louis Hodges
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76
CPC分类号： H01L29/66757 , H01L29/78624
摘要： A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode. Due to the difference in diffusion rates between the relatively slow-diffusing dopant and the relatively fast-diffusing dopant, a transistor having a drain junction offset is formed.
摘要翻译：制造集成电路晶体管的方法开始于在导电层上生长的绝缘层上形成栅电极。侧壁间隔物沿着栅电极的垂直边缘形成，并且掩模施加到漏极区域。然后将相对快速扩散的掺杂剂注入到导电层中的源极区域中。此后，去除掩模，并用较慢扩散的掺杂剂注入漏区。最后，导电层被退火，导致相对快速扩散的掺杂剂在源侧壁间隔物下方扩散到栅电极的源极侧的垂直边缘附近的位置，并使相对较慢的扩散掺杂剂在下面延伸漏极侧壁间隔较小的距离，使得漏极结与栅极下方横向间隔开。由于相对较慢扩散的掺杂剂和相对快速扩散的掺杂剂之间的扩散速率的差异，形成具有漏极结偏移的晶体管。

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