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1. 发明授权

US5632028A Hardware support for fast software emulation of unimplemented instructions 失效
标题翻译：硬件支持快速软件仿真未实现的指令
公开(公告)号：US5632028A
公开(公告)日：1997-05-20
申请号：US397911
申请日：1995-03-03
申请人： Shalesh Thusoo , Farnad Sajjadian , Jaspal Kohli , Niteen A. Patkar
发明人： Shalesh Thusoo , Farnad Sajjadian , Jaspal Kohli , Niteen A. Patkar
IPC分类号： G06F9/30 , G06F9/455 , G06F3/00
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/45533
摘要： A system and method provides hardware support for fast software emulation of unimplemented instructions using issue trap logic that determines the instruction type and parameter fields of an unimplemented instruction when an exception is triggered and uses the fields to branch directly to emulation code specific to an unimplemented instruction having the determined instruction type and parameter fields.
摘要翻译：系统和方法提供硬件支持，使用问题陷阱逻辑来快速软件仿真未实现的指令，该逻辑确定当异常被触发时未实现的指令的指令类型和参数字段，并使用这些字段直接转移到未实现指令特有的仿真代码具有确定的指令类型和参数字段。

2. 发明授权

US5838940A Method and apparatus for rotating active instructions in a parallel data processor 失效
标题翻译：用于在并行数据处理器中旋转主动指令的方法和装置
公开(公告)号：US5838940A
公开(公告)日：1998-11-17
申请号：US926185
申请日：1997-09-08
申请人： Sunil Savkar , Michael C. Shebanow , Gene W. Shen , Farnad Sajjadian
发明人： Sunil Savkar , Michael C. Shebanow , Gene W. Shen , Farnad Sajjadian
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： In a microprocessor, apparatus and method coordinate the fetch and issue of instructions by rotating multiple, fetched instructions into an issue order prior to issuance and dispatching selected of the issue ordered instructions. The rotate and dispatch block including a mixer for mixing newly fetched instructions with previously fetched and unissued instructions in physical memory order, a mix and rotate device for rotating the mixed instructions into issue order, an instruction latch for holding the issue ordered instructions prior to dispatch, and an unrotate device for rotating non-issued instructions from issue order to physical memory order prior to mixing with newly fetched instructions. During the fetch cycle, multiple instructions are simultaneously fetched from storage in physical memory order and rotated into a PC-related issue order within the rotate and dispatch block. During the next clock cycle, selected ones of the previously fetched and rotated instructions enter the issue cycle, a new set of instructions are fetched in physical memory order, the previously fetched and rotated instructions which were not issued are rearranged into physical memory order and mixed in physical memory order with the newly fetched instructions, together all fetched and non-issued instructions are rotated into issue order prior to the next issue cycle, and so forth until all instructions have passed through the pipeline.
摘要翻译：在微处理器中，装置和方法通过在发出和发送所选问题排序的指令之前将多个获取的指令旋转到发布顺序来协调提取和发出指令。旋转和调度块包括用于将新获取的指令与物理存储器顺序中的先前取出和未发布的指令混合的混合器，用于将混合指令转换成发行订单的混合和旋转装置，用于在调度之前保持发出有序指令的指令锁存器以及用于在与新获取的指令混合之前将未发布指令从发布顺序旋转到物理存储器顺序的非旋转装置。在读取周期期间，多个指令以物理存储器顺序从存储器中同时提取，并在旋转和调度块内旋转成与PC相关的问题顺序。在下一个时钟周期中，先前提取和旋转的指令中选定的指令进入发布周期，以物理存储器顺序取出一组新的指令，将未发出的先前提取和转换的指令重新排列成物理内存顺序并进行混合在具有新获取的指令的物理存储器顺序中，将所有获取的和未发布的指令一起在下一个发布周期之前旋转成发行顺序，等等，直到所有指令都通过流水线。

3. 发明申请

US20080222396A1 Low Overhead Access to Shared On-Chip Hardware Accelerator With Memory-Based Interfaces 有权
标题翻译：具有基于内存接口的共享片上硬件加速器的低架构访问
公开(公告)号：US20080222396A1
公开(公告)日：2008-09-11
申请号：US11684348
申请日：2007-03-09
申请人： Lawrence A. Spracklen , Adam R. Talcott , Santosh G. Abraham , Sothea Soun , Sanjay Patel , Farnad Sajjadian
发明人： Lawrence A. Spracklen , Adam R. Talcott , Santosh G. Abraham , Sothea Soun , Sanjay Patel , Farnad Sajjadian
IPC分类号： G06F9/50
CPC分类号： G06F21/71 , G06F12/1027 , G06F2212/683
摘要： In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.
摘要翻译：在一个实施例中，预期了一种方法。用户特权线程请求访问硬件加速器。通过响应请求的较高特权线程向硬件加速器的访问授予用户特权线程。一个或多个命令由用户特权的线程传送到硬件加速器，而不受较高特权线程的干扰，并响应于授权的访问。一个或多个命令使硬件加速器执行一个或多个任务。计算机可读介质包括当各种实施例中被执行时实施该方法的部分的指令，以及硬件加速器和耦合到硬件加速器的处理器。

4. 发明授权

US08762951B1 Apparatus and method for profiling system events in a fine grain multi-threaded multi-core processor 有权
标题翻译：在细粒度多线程多核处理器中对系统事件进行分析的装置和方法
公开(公告)号：US08762951B1
公开(公告)日：2014-06-24
申请号：US11689359
申请日：2007-03-21
申请人： Nicolai Kosche , James P. Laudon , Adam R. Talcott , Sanjay Patel , Farnad Sajjadian
发明人： Nicolai Kosche , James P. Laudon , Adam R. Talcott , Sanjay Patel , Farnad Sajjadian
IPC分类号： G06F9/44
CPC分类号： G06F11/3476 , G06F8/443 , G06F11/3409 , G06F2201/86 , G06F2201/865 , G06F2201/87 , G06F2201/88
摘要： A system and method for profiling runtime system events of a computer system may include associating a data source type with detected system events. The system events may be detected dependent on information included in a reply message received by a processor in response to a data request or other transaction request message. The reply message may include information characterizing a source type of a source of data included in the reply message. The source type information may indicate that the source is remote or local; that it is a shared or a private storage location; that the data is supplied via a cache-to-cache transfer; or that the data is sourced from a coherency domain other than that of the requesting process. Instructions, events, messages, and replies may be sampled, and extended address information corresponding to the samples may be stored in an event set database for performance analysis.
摘要翻译：用于分析计算机系统的运行时系统事件的系统和方法可以包括将数据源类型与检测到的系统事件相关联。可以根据由处理器响应于数据请求或其他事务请求消息而接收到的应答消息中包括的信息来检测系统事件。回复消息可以包括表征包括在回复消息中的数据源的源类型的信息。源类型信息可以指示源是远程的或本地的; 它是一个共享或私人存储位置; 数据通过缓存到缓存传输提供; 或者数据来自与请求进程的一致性域之外的一致性域。可以对指令，事件，消息和答复进行采样，并且与样本相对应的扩展地址信息可以存储在用于性能分析的事件集数据库中。

5. 发明授权

US07809895B2 Low overhead access to shared on-chip hardware accelerator with memory-based interfaces 有权
标题翻译：具有基于内存的接口的共享片上硬件加速器的低开销访问
公开(公告)号：US07809895B2
公开(公告)日：2010-10-05
申请号：US11684348
申请日：2007-03-09
申请人： Lawrence A. Spracklen , Adam R. Talcott , Santosh G. Abraham , Sothea Soun , Sanjay Patel , Farnad Sajjadian
发明人： Lawrence A. Spracklen , Adam R. Talcott , Santosh G. Abraham , Sothea Soun , Sanjay Patel , Farnad Sajjadian
IPC分类号： G06F12/14 , G06F13/00 , G06F15/82
CPC分类号： G06F21/71 , G06F12/1027 , G06F2212/683
摘要： In one embodiment, a method is contemplated. Access to a hardware accelerator is requested by a user-privileged thread. Access to the hardware accelerator is granted to the user-privileged thread by a higher-privileged thread responsive to the requesting. One or more commands are communicated to the hardware accelerator by the user-privileged thread without intervention by higher-privileged threads and responsive to the grant of access. The one or more commands cause the hardware accelerator to perform one or more tasks. Computer readable media comprises instructions which, when executed, implement portions of the method are also contemplated in various embodiments, as is a hardware accelerator and a processor coupled to the hardware accelerator.
摘要翻译：在一个实施例中，预期了一种方法。用户特权线程请求访问硬件加速器。通过响应请求的较高特权线程向硬件加速器的访问授予用户特权线程。一个或多个命令由用户特权的线程传送到硬件加速器，而不受较高特权线程的干扰，并响应于授权的访问。一个或多个命令使硬件加速器执行一个或多个任务。计算机可读介质包括当各种实施例中被执行时实施该方法的部分的指令，以及硬件加速器和耦合到硬件加速器的处理器。

6. 发明申请

US20110091035A1 HARDWARE KASUMI CYPHER WITH HYBRID SOFTWARE INTERFACE 审中-公开
标题翻译：具有混合软件接口的硬件KASUMI CYPHER
公开(公告)号：US20110091035A1
公开(公告)日：2011-04-21
申请号：US12582299
申请日：2009-10-20
申请人： Lawrence Spracklen , Farnad Sajjadian , Christopher H. Olson , Sanjay Patel
发明人： Lawrence Spracklen , Farnad Sajjadian , Christopher H. Olson , Sanjay Patel
IPC分类号： H04L9/18
CPC分类号： H04L9/0625 , H04L2209/12 , H04L2209/20 , H04L2209/80 , H04W12/02 , H04W12/10
摘要： A system including a memory; a software interface, operatively connected to the memory, and configured to generate a modified version of a confidentially key (CKey), and a modified version of an integrity key (IKey); and a Kasumi engine having a hardware implementation of a Kasumi cipher and configured to load the modified version of the CKey from the memory to perform a confidentiality function, and to load the modified version of the IKey from memory to perform an integrity function.
摘要翻译：包括存储器的系统; 软件接口，可操作地连接到存储器，并被配置为生成保密键（CKey）的修改版本和完整性密钥（IKey）的修改版本; 以及具有Kasumi密码的硬件实现的Kasumi引擎，并且被配置为从存储器加载CKey的修改版本以执行机密功能，并且从存储器加载IKey的修改版本以执行完整性功能。

7. 发明授权

US5896526A Programmable instruction trap system and method 失效
标题翻译：可编程指令陷阱系统和方法
公开(公告)号：US5896526A
公开(公告)日：1999-04-20
申请号：US25511
申请日：1998-02-18
申请人： Sunil Savkar , Gene W. Shen , Farnad Sajjadian , Michael C. Shebanow
发明人： Sunil Savkar , Gene W. Shen , Farnad Sajjadian , Michael C. Shebanow
IPC分类号： G06F9/38 , G06F9/30 , G06F11/28 , G06F11/36 , G06F11/00
CPC分类号： G06F11/3648
摘要： A system and method providing a programmable hardware device within a CPU. The programmable hardware device permits a plurality of instructions to be trapped before they are executed. The instructions that are to be trapped are programmable to provide flexibility during CPU debugging and to ensure that a variety of application programs can be properly executed by the CPU. The system must also provide a means for permitting a trapped instruction to be emulated and/or to be executed serially. Related Applications
摘要翻译：一种在CPU内提供可编程硬件设备的系统和方法。可编程硬件设备允许在执行多个指令之前被捕获。要被捕获的指令是可编程的，以便在CPU调试期间提供灵活性，并确保CPU可以正确执行各种应用程序。该系统还必须提供一种允许被捕获的指令被仿真和/或串行执行的手段。相关应用

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