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1. 发明申请

US20090294748A1 Phase Change Memory Cell with Reduced Switchable Volume 有权
标题翻译：具有可切换容积的相变存储器单元
公开(公告)号：US20090294748A1
公开(公告)日：2009-12-03
申请号：US12498840
申请日：2009-07-07
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1666
摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
摘要翻译：通过形成电介质层并在电介质层中构图孔来制造存储单元。至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。图案化介电层的至少一部分保留在最终存储单元中。

2. 发明授权

US08426967B2 Scaled-down phase change memory cell in recessed heater 有权
标题翻译：嵌入式加热器中的缩小相变存储单元
公开(公告)号：US08426967B2
公开(公告)日：2013-04-23
申请号：US11620138
申请日：2007-01-05
申请人： Eric Andrew Joseph , Chung Hon Lam , Alejandro Gabriel Schrott
发明人： Eric Andrew Joseph , Chung Hon Lam , Alejandro Gabriel Schrott
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/06
CPC分类号： H01L45/1233 , H01L27/2436 , H01L45/06 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.
摘要翻译：可配置为用作非易失性存储元件的半导体结构包括第一电极，形成在第一电极的上表面的至少一部分上的绝缘层和穿过绝缘层并且相对于第一电极的上表面凹陷的柱绝缘层。支柱包括形成在第一电极的上表面的至少一部分上的加热器和形成在靠近加热器的绝缘层的侧壁上和在加热器的上表面的至少一部分上的套环。该结构还包括形成在绝缘层的上表面的至少一部分上并基本上填充由加热器的上表面限定的体积和套环的上表面的至少一部分的PCM层。第二电极形成在相变材料层的上表面的至少一部分上。

3. 发明授权

US08138028B2 Method for manufacturing a phase change memory device with pillar bottom electrode 有权
标题翻译：具有柱底电极的相变存储器件的制造方法
公开(公告)号：US08138028B2
公开(公告)日：2012-03-20
申请号：US11764678
申请日：2007-06-18
申请人： Hsiang Lan Lung , Chieh Fang Chen , Yi Chou Chen , Shih Hung Chen , Chung Hon Lam , Eric Andrew Joseph , Alejandro Gabriel Schrott , Matthew J. Breitwisch , Geoffrey William Burr , Thomas D. Happ , Jan Boris Philipp
发明人： Hsiang Lan Lung , Chieh Fang Chen , Yi Chou Chen , Shih Hung Chen , Chung Hon Lam , Eric Andrew Joseph , Alejandro Gabriel Schrott , Matthew J. Breitwisch , Geoffrey William Burr , Thomas D. Happ , Jan Boris Philipp
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
摘要翻译：用于制造蘑菇细胞型相变存储器的方法是基于在包括与接入电路电连通的导电触点阵列的基板上制造底部电极材料的柱。沉积一层电极材料，使其与导电触点阵列可靠地电接触。蚀刻电极材料以在对应的导电触点上形成电极柱的图案。接下来，将介电材料沉积在图案上并且被平坦化以提供暴露电极柱顶表面的电极表面。接下来，沉积诸如硫族化物或其它相变材料的可编程电阻材料层，随后沉积顶层电极材料层。描述了包括具有比顶表面更大的底表面的底部电极柱的装置。

4. 发明授权

US08115186B2 Phase change memory cell with reduced switchable volume 有权
标题翻译：相变容量小的相变存储单元
公开(公告)号：US08115186B2
公开(公告)日：2012-02-14
申请号：US12498840
申请日：2009-07-07
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/144 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1666
摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
摘要翻译：通过形成电介质层并在电介质层中构图孔来制造存储单元。至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。图案化介电层的至少一部分保留在最终存储单元中。

5. 发明申请

US20080265234A1 Method of Forming Phase Change Memory Cell With Reduced Switchable Volume 审中-公开
标题翻译：形成具有可切换容积的相变存储单元的方法
公开(公告)号：US20080265234A1
公开(公告)日：2008-10-30
申请号：US11741781
申请日：2007-04-30
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1666
摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
摘要翻译：通过形成电介质层并在电介质层中构图孔来制造存储单元。至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。图案化介电层的至少一部分保留在最终存储单元中。

6. 发明申请

US20080164452A1 Scaled-Down Phase Change Memory Cell in Recessed Heater 有权
标题翻译：嵌入式加热器中的缩小相变存储单元
公开(公告)号：US20080164452A1
公开(公告)日：2008-07-10
申请号：US11620138
申请日：2007-01-05
申请人： Eric Andrew Joseph , Chung Hon Lam , Alejandro Gabriel Schrott
发明人： Eric Andrew Joseph , Chung Hon Lam , Alejandro Gabriel Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , H01L27/2436 , H01L45/06 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/148 , H01L45/1691
摘要： A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.
摘要翻译：可配置为用作非易失性存储元件的半导体结构包括第一电极，形成在第一电极的上表面的至少一部分上的绝缘层和穿过绝缘层并且相对于第一电极的上表面凹陷的柱绝缘层。支柱包括形成在第一电极的上表面的至少一部分上的加热器和形成在靠近加热器的绝缘层的侧壁上和在加热器的上表面的至少一部分上的套环。该结构还包括形成在绝缘层的上表面的至少一部分上并基本上填充由加热器的上表面限定的体积和套环的上表面的至少一部分的PCM层。第二电极形成在相变材料层的上表面的至少一部分上。

7. 发明申请

US20090261313A1 MEMORY CELL HAVING A BURIED PHASE CHANGE REGION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有相位变化区域的存储单元及其制造方法
公开(公告)号：US20090261313A1
公开(公告)日：2009-10-22
申请号：US12107573
申请日：2008-04-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro Gabriel Schrott
发明人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro Gabriel Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1666
摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.
摘要翻译：描述存储单元以及制造方法。本文所述的存储单元包括底部电极，其包括基部和基部上的柱部，所述柱部的宽度小于基部的宽度。电介质围绕底部电极并具有顶部表面。存储元件覆盖在底部电极上，并且包括从电介质的顶表面延伸以与底部电极的柱部分接触的凹部，其中存储元件的凹部的宽度基本上等于柱的宽度部分底部电极。顶部电极位于存储元件上。

8. 发明申请

US20090186443A1 METHOD TO ENHANCE PERFORMANCE OF COMPLEX METAL OXIDE PROGRAMMABLE MEMORY 审中-公开
标题翻译：提高复合金属氧化物可编程存储器性能的方法
公开(公告)号：US20090186443A1
公开(公告)日：2009-07-23
申请号：US12017848
申请日：2008-01-22
申请人： Eric A. Joseph , Chung Hon Lam , Gerhard I. Meijer , Stephen M. Rossnagel , Alejandro Gabriel Schrott
发明人： Eric A. Joseph , Chung Hon Lam , Gerhard I. Meijer , Stephen M. Rossnagel , Alejandro Gabriel Schrott
IPC分类号： H01L21/34
CPC分类号： H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/147 , H01L45/16
摘要： A method of incorporating oxygen vacancies near an electrode/oxide interface region of a complex metal oxide programmable memory cell which includes forming a first electrode of a metallic material which remains metallic upon oxidation, forming a second electrode facing the first electrode, forming an oxide layer in between the first and second electrodes, applying an electrical signal to the first electrode such that oxygen ions from the oxide layer are embedded in and oxidize the first electrode, and forming oxygen vacancies near the electrode/oxide interface region of the complex metal oxide programmable memory cell.
摘要翻译：一种在复合金属氧化物可编程存储单元的电极/氧化物界面区域附近引入氧空位的方法，其包括在氧化时形成保持金属的金属材料的第一电极，形成面向第一电极的第二电极，形成氧化物层在第一和第二电极之间，向第一电极施加电信号，使得来自氧化物层的氧离子嵌入并氧化第一电极，并在复合金属氧化物可编程的电极/氧化物界面区域附近形成氧空位记忆单元

9. 发明授权

US07989796B2 Nonvolatile memory cell with concentric phase change material formed around a pillar arrangement 有权
标题翻译：具有同心相变材料的非易失性存储单元围绕柱布置形成
公开(公告)号：US07989796B2
公开(公告)日：2011-08-02
申请号：US12051389
申请日：2008-03-19
申请人： Chung Hon Lam , Alejandro Gabriel Schrott
发明人： Chung Hon Lam , Alejandro Gabriel Schrott
IPC分类号： H01L47/00
CPC分类号： H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1691
摘要： A memory cell comprises a first feature and a second feature. The second feature comprises a dielectric material and defines an opening at least partially overlying the first feature. A third feature is formed on the first feature and partially fills the opening in the second feature. What is more, a phase change material at least fills a volume between the second feature and the third feature. At least a portion of the phase change material is operative to switch between lower and higher electrical resistance states in response to an application of a switching signal to the memory cell.
摘要翻译：存储单元包括第一特征和第二特征。第二特征包括介电材料并限定至少部分地覆盖第一特征的开口。在第一特征上形成第三特征并且部分地填充第二特征中的开口。此外，相变材料至少填充第二特征和第三特征之间的体积。响应于将切换信号施加到存储器单元，相变材料的至少一部分可操作以在较低和较高的电阻状态之间切换。

10. 发明授权

US08012793B2 Nonvolatile memory cell comprising a chalcogenide and a transition metal oxide 有权
标题翻译：包含硫族化物和过渡金属氧化物的非挥发性存储单元
公开(公告)号：US08012793B2
公开(公告)日：2011-09-06
申请号：US12509889
申请日：2009-07-27
申请人： Chung Hon Lam , Gerhard Ingmar Meijer , Alejandro Gabriel Schrott
发明人： Chung Hon Lam , Gerhard Ingmar Meijer , Alejandro Gabriel Schrott
IPC分类号： H01L21/06
CPC分类号： H01L45/145 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C2213/32 , H01L45/04
摘要： A memory cell for use in integrated circuits comprises a chalcogenide feature and a transition metal oxide feature. Both the chalcogenide feature and transition metal oxide feature each have at least two stable electrical resistance states. At least two bits of data can be concurrently stored in the memory cell by placing the chalcogenide feature into one of its stable electrical resistance states and by placing the transition metal oxide feature into one of its stable electrical resistance states.
摘要翻译：用于集成电路的存储单元包括硫族化物特征和过渡金属氧化物特征。硫族化物特征和过渡金属氧化物特征都具有至少两个稳定的电阻状态。通过将硫族化物特征置于其稳定的电阻状态之一并且将过渡金属氧化物特征置于其稳定的电阻状态之一中，可将至少两位数据同时存储在存储单元中。

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