专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07817761B2 Test techniques for a delay-locked loop receiver interface 有权
标题翻译：延迟锁定环路接收机接口的测试技术
公开(公告)号：US07817761B2
公开(公告)日：2010-10-19
申请号：US11756674
申请日：2007-06-01
申请人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： G01R31/3016 , G01R31/31725 , H03L7/07 , H03L7/0814 , H03L7/091
摘要： An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
摘要翻译：集成电路包括可变延迟电路，其被配置为基于第一时钟信号和第一控制信号产生至少一个延迟的时钟信号。集成电路包括配置为基于第二输入信号和第二控制信号产生计数值的控制电路。第一时钟信号是至少一个延迟时钟信号的第一版本。所述第二输入信号和所述第二控制信号中的至少一个是所述至少一个延迟时钟信号的第二版本，并且所述计数值指示所述至少一个延迟的时钟信号的频率特性。集成电路被配置为在一个值的范围内单调地改变第一控制信号，并且针对控制信号的各个值确定计数值。

2. 发明申请

US20120166899A1 FAULT TOLERANT SCANNABLE GLITCH LATCH 有权
标题翻译：容错扫帚锁
公开(公告)号：US20120166899A1
公开(公告)日：2012-06-28
申请号：US12976170
申请日：2010-12-22
申请人： Kevin M. Gillespie , Joseph R. Siegel , Dwight K. Elvey , Harry R. Fair
发明人： Kevin M. Gillespie , Joseph R. Siegel , Dwight K. Elvey , Harry R. Fair
IPC分类号： G06F11/00
CPC分类号： G01R31/318541
摘要： A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.
摘要翻译：描述了一种与扫描链一起使用的容错可扫描毛刺锁，可实现机床和零件的复位，调试和修复。扫描移位使能信号控制开关，使得在扫描链操作期间，防止数据输入线上的卡入零故障驱动电压到状态节点或拉高状态节点。因此消除了卡住零故障的传播。扫描移位使能信号还控制一个开关，该开关使扫描数据和状态节点的并联路径能够由于卡住的零故障而被驱动为高电平。

3. 发明授权

US07685487B1 Simultaneous core testing in multi-core integrated circuits 有权
标题翻译：多核心集成电路同时核心测试
公开(公告)号：US07685487B1
公开(公告)日：2010-03-23
申请号：US11086924
申请日：2005-03-22
申请人： Ting-Yu Kuo , Dwight K. Elvey
发明人： Ting-Yu Kuo , Dwight K. Elvey
IPC分类号： G01R31/28
CPC分类号： G01R31/318563
摘要： Various embodiments of methods and systems for simultaneously testing multiple cores included in an integrated circuit are disclosed. In one embodiment, an integrated circuit may include two or more logic cores. The IC may also include structural scan test hardware coupled to the cores. This structural scan test hardware may be capable of inputting scan test vector data into scan registers associated with each of the logic cores, simultaneously executing a scan test on the logic cores included in the IC, and outputting the results of the scan tests for multiple cores to automated test equipment (ATE) simultaneously. In one embodiment, elements of the results of testing for multiple cores may be interleaved on a single output line such that an element of test result data from each core is present on an input channel to the ATE during each strobe window.
摘要翻译：公开了用于同时测试集成电路中包括的多个核的方法和系统的各种实施例。在一个实施例中，集成电路可以包括两个或更多个逻辑核。 IC还可以包括耦合到核的结构扫描测试硬件。该结构扫描测试硬件可能能够将扫描测试矢量数据输入到与每个逻辑核心相关联的扫描寄存器中，同时对包含在IC中的逻辑核心执行扫描测试，并输出多个核心的扫描测试结果同时进行自动化测试设备（ATE）。在一个实施例中，用于多个核心的测试结果的元素可以交织在单个输出线上，使得来自每个核心的测试结果数据的元素在每个选通窗口期间的输入信道上存在于ATE。

4. 发明申请

US20080297216A1 TEST TECHNIQUES FOR A DELAY-LOCKED LOOP RECEIVER INTERFACE 有权
标题翻译：延迟环路接收机接口的测试技术
公开(公告)号：US20080297216A1
公开(公告)日：2008-12-04
申请号：US11756674
申请日：2007-06-01
申请人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03L7/06 , G01R31/28
CPC分类号： G01R31/3016 , G01R31/31725 , H03L7/07 , H03L7/0814 , H03L7/091
摘要： An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
摘要翻译：集成电路包括可变延迟电路，其被配置为基于第一时钟信号和第一控制信号产生至少一个延迟的时钟信号。集成电路包括配置为基于第二输入信号和第二控制信号产生计数值的控制电路。第一时钟信号是至少一个延迟时钟信号的第一版本。所述第二输入信号和所述第二控制信号中的至少一个是所述至少一个延迟时钟信号的第二版本，并且所述计数值指示所述至少一个延迟的时钟信号的频率特性。集成电路被配置为在一个值的范围内单调地改变第一控制信号，并且针对控制信号的各个值确定计数值。

5. 发明授权

US08850278B2 Fault tolerant scannable glitch latch 有权
标题翻译：容错可扫描毛刺锁
公开(公告)号：US08850278B2
公开(公告)日：2014-09-30
申请号：US12976170
申请日：2010-12-22
申请人： Kevin M. Gillespie , Joseph R. Siegel , Dwight K. Elvey , Harry R. Fair
发明人： Kevin M. Gillespie , Joseph R. Siegel , Dwight K. Elvey , Harry R. Fair
IPC分类号： G06F11/00 , G01R31/3185
CPC分类号： G01R31/318541
摘要： A fault tolerant scannable glitch latch for use with scan chains that enable reset, debug and repairability of machines and parts is described. A scan shift enable signal controls a switch such that a stuck-at zero fault on a data input line is prevented from driving voltage to a state node or pulling the state node high during a scan chain operation. Propagation of the stuck-at zero fault is therefore eliminated. The scan shift enable signal also controls a switch that enables a parallel path to ground for the scan data and state node which would otherwise have been driven high due to the stuck-at zero fault.
摘要翻译：描述了一种与扫描链一起使用的容错可扫描毛刺锁，可实现机床和零件的复位，调试和修复。扫描移位使能信号控制开关，使得在扫描链操作期间，防止数据输入线上的卡入零故障驱动电压到状态节点或拉高状态节点。因此消除了卡住零故障的传播。扫描移位使能信号还控制一个开关，该开关使扫描数据和状态节点的并联路径能够由于卡住的零故障而被驱动为高电平。

6. 发明授权

US08461874B2 Preventing A-B-A race in a latch-based device 有权
公开(公告)号：US08461874B2
公开(公告)日：2013-06-11
申请号：US13187163
申请日：2011-07-20
申请人： Dwight K. Elvey , Premlatha Paga
发明人： Dwight K. Elvey , Someshwar Gatty
IPC分类号： H03K19/20
CPC分类号： H03K19/096 , G06F1/3237 , G06F17/505 , G06F2217/78 , H03K19/0016 , Y02D10/128
摘要： A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.

7. 发明申请

US20130021064A1 PREVENTING A-B-A RACE IN A LATCH-BASED DEVICE 有权
公开(公告)号：US20130021064A1
公开(公告)日：2013-01-24
申请号：US13187163
申请日：2011-07-20
申请人： Dwight K. Elvey , Premlatha Paga
发明人： Dwight K. Elvey , Someshwar Gatty
IPC分类号： H03K19/20
CPC分类号： H03K19/096 , G06F1/3237 , G06F17/505 , G06F2217/78 , H03K19/0016 , Y02D10/128
摘要： A device may include a latch activated during a second phase of a clock cycle; a clock gating component to control when a clock signal is to reach the latch; a destination storage element activated during a first phase of the clock cycle, where a logical path exists from the latch to the destination storage element; and a blocking element located in the logical path from the latch to the destination storage element, where the blocking element includes, as a first input, an output of the latch and, as a second input, an output of the clock gating component, and where the blocking element prevents an output value of the latch from changing when the clock gating component is not enabled and does not prevent the output value of the latch from changing when the clock gating element is enabled.

8. 发明授权

US06636997B1 System and method for improving LBIST test coverage 有权
标题翻译： LBIST测试覆盖的系统和方法
公开(公告)号：US06636997B1
公开(公告)日：2003-10-21
申请号：US09695749
申请日：2000-10-24
申请人： Paul Wong , Mark O. Porter , Dwight K. Elvey
发明人： Paul Wong , Mark O. Porter , Dwight K. Elvey
IPC分类号： G01R3128
CPC分类号： G01R31/318536 , G01R31/318566
摘要： The initialization process and structure of the system ensure that during loading of random data a 1-hot condition is maintained to the 1-hot multiplexer so as to prevent contention or a high current state. The present invention further improves observability of intermediate stages by preventing random data feeding of the state elements in scan chains that cannot tolerate random data. A scan chain having only scan registers that can receive random data is referred to as a LBIST Random Scan Chain (LRSC) and a scan chain having one or more scan registers that cannot tolerate and cannot receive random data is referred to as a “LBIST Non-random Scan Chain” (LNSC). A PRPG generates random data having a plurality of bit values to the LRSCs which is then passed to a multiple input shift register (MISR). The LNSCs do not receive random data from the PRPG but instead receive bit values from another scan chain. Before feeding bit values into a LNSC, the bit values are feed into a decoder and the LNSCs feed bit values reflecting test responses into the MISR. The system may further include recirculation lines in electrical communication with a LNSC to recirculate original bit values back into the LNSC.
摘要翻译：系统的初始化过程和结构确保在加载随机数据期间，保持1-hot条件到1-hot多路复用器，以防止争用或高电流状态。本发明通过防止在不能容忍随机数据的扫描链中的状态元素的随机数据馈送来进一步提高中间级的可观察性。具有仅能够接收随机数据的扫描寄存器的扫描链被称为LBIST随机扫描链（LRSC），并且具有不能容忍和不能接收随机数据的一个或多个扫描寄存器的扫描链被称为“LBIST非 - 随机扫描链“（LNSC）。 PRPG向LRSC生成具有多个比特值的随机数据，然后将其传递给多输入移位寄存器（MISR）。 LNSC不会从PRPG接收随机数据，而是从另一个扫描链接收位值。在将位值送入LNSC之前，将位值送入解码器，LNSC将反映测试响应的位值送入MISR。该系统还可以包括与LNSC电连通的再循环线，以将原始比特值再循环回LNSC。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式