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1. 发明授权

US07817761B2 Test techniques for a delay-locked loop receiver interface 有权
标题翻译：延迟锁定环路接收机接口的测试技术
公开(公告)号：US07817761B2
公开(公告)日：2010-10-19
申请号：US11756674
申请日：2007-06-01
申请人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： G01R31/3016 , G01R31/31725 , H03L7/07 , H03L7/0814 , H03L7/091
摘要： An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
摘要翻译：集成电路包括可变延迟电路，其被配置为基于第一时钟信号和第一控制信号产生至少一个延迟的时钟信号。集成电路包括配置为基于第二输入信号和第二控制信号产生计数值的控制电路。第一时钟信号是至少一个延迟时钟信号的第一版本。所述第二输入信号和所述第二控制信号中的至少一个是所述至少一个延迟时钟信号的第二版本，并且所述计数值指示所述至少一个延迟的时钟信号的频率特性。集成电路被配置为在一个值的范围内单调地改变第一控制信号，并且针对控制信号的各个值确定计数值。

2. 发明申请

US20080297216A1 TEST TECHNIQUES FOR A DELAY-LOCKED LOOP RECEIVER INTERFACE 有权
标题翻译：延迟环路接收机接口的测试技术
公开(公告)号：US20080297216A1
公开(公告)日：2008-12-04
申请号：US11756674
申请日：2007-06-01
申请人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03L7/06 , G01R31/28
CPC分类号： G01R31/3016 , G01R31/31725 , H03L7/07 , H03L7/0814 , H03L7/091
摘要： An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
摘要翻译：集成电路包括可变延迟电路，其被配置为基于第一时钟信号和第一控制信号产生至少一个延迟的时钟信号。集成电路包括配置为基于第二输入信号和第二控制信号产生计数值的控制电路。第一时钟信号是至少一个延迟时钟信号的第一版本。所述第二输入信号和所述第二控制信号中的至少一个是所述至少一个延迟时钟信号的第二版本，并且所述计数值指示所述至少一个延迟的时钟信号的频率特性。集成电路被配置为在一个值的范围内单调地改变第一控制信号，并且针对控制信号的各个值确定计数值。

3. 发明申请

US20080273528A1 PHASE SELECT CIRCUIT WITH REDUCED HYSTERESIS EFFECT 有权
标题翻译：相位选择电路具有减少的滞后效应
公开(公告)号：US20080273528A1
公开(公告)日：2008-11-06
申请号：US11742860
申请日：2007-05-01
申请人： Sanjeev Maheshwari , Meei-Ling Chiang , Emerson S. Fang
发明人： Sanjeev Maheshwari , Meei-Ling Chiang , Emerson S. Fang
IPC分类号： H04L12/50
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0814 , H04L7/0008 , H04L7/0025
摘要： A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.
摘要翻译：相位信号选择电路包括耦合到三态反相器电路的支撑路径。支持路径减少了滞后对信号传输的影响。一种装置包括响应于至少一个输入信号中的相应一个的至少一个输入节点。该装置包括耦合到至少一个输入节点中的相应一个并耦合到输出节点的至少一个电路。所述至少一个电路中的各个电路被配置为响应于相应选择信号的第一状态而将相应输入信号的形式提供给输出节点。该装置包括耦合到至少一个电路中的相应一个电路的至少一个第二电路。至少一个第二电路被配置为响应于相应选择信号的第二状态来切换至少一个电路的节点。

4. 发明申请

US20080272814A1 PARALLEL MULTIPLEXING DUTY CYCLE ADJUSTMENT CIRCUIT WITH PROGRAMMABLE RANGE CONTROL 有权
标题翻译：具有可编程范围控制的并行多路复用占空比调整电路
公开(公告)号：US20080272814A1
公开(公告)日：2008-11-06
申请号：US11742845
申请日：2007-05-01
申请人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.
摘要翻译：接收接口电路包括占空比调整电路，其至少部分地基于选定数量的占空比调整单元和所选择的占空比调整范围来调整参考时钟信号的占空比。占空比调整电路可以与占空比调整并行地选择时钟信号和至少较低版本的时钟信号之一作为参考时钟信号。

5. 发明授权

US07750711B2 Phase select circuit with reduced hysteresis effect 有权
标题翻译：具有减小滞后效应的相位选择电路
公开(公告)号：US07750711B2
公开(公告)日：2010-07-06
申请号：US11742860
申请日：2007-05-01
申请人： Sanjeev Maheshwari , Meei-Ling Chiang , Emerson S. Fang
发明人： Sanjeev Maheshwari , Meei-Ling Chiang , Emerson S. Fang
IPC分类号： H03H11/26
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0814 , H04L7/0008 , H04L7/0025
摘要： A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.
摘要翻译：相位信号选择电路包括耦合到三态反相器电路的支撑通路。支持路径减少了滞后对信号传输的影响。一种装置包括响应于至少一个输入信号中的相应一个的至少一个输入节点。该装置包括耦合到至少一个输入节点中的相应一个并耦合到输出节点的至少一个电路。所述至少一个电路中的各个电路被配置为响应于相应选择信号的第一状态而将相应输入信号的形式提供给输出节点。该装置包括耦合到至少一个电路中的相应一个电路的至少一个第二电路。至少一个第二电路被配置为响应于相应选择信号的第二状态来切换至少一个电路的节点。

6. 发明授权

US07545190B2 Parallel multiplexing duty cycle adjustment circuit with programmable range control 有权
标题翻译：并行多路复用占空比调节电路，具有可编程范围控制
公开(公告)号：US07545190B2
公开(公告)日：2009-06-09
申请号：US11742845
申请日：2007-05-01
申请人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.
摘要翻译：接收接口电路包括占空比调整电路，其至少部分地基于选定数量的占空比调整单元和所选择的占空比调整范围来调整参考时钟信号的占空比。占空比调整电路可以与占空比调整并行地选择时钟信号和至少较低版本的时钟信号之一作为参考时钟信号。

7. 发明申请

US20140049292A1 INTEGRATED CIRCUIT PACKAGE HAVING MEDIUM-INDEPENDENT SIGNALING INTERFACE COUPLED TO CONNECTOR ASSEMBLY 审中-公开
标题翻译：具有中型独立信号接口的集成电路封装与连接器总成相连
公开(公告)号：US20140049292A1
公开(公告)日：2014-02-20
申请号：US13588704
申请日：2012-08-17
申请人： Petre Popescu , Emerson S. Fang , Bruce A. Doyle , Alvin Leng Sun Loke , Shawn Searles
发明人： Petre Popescu , Emerson S. Fang , Bruce A. Doyle , Alvin Leng Sun Loke , Shawn Searles
IPC分类号： H01R12/70 , G02B6/36 , H03K5/01
CPC分类号： G02B6/43 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48227 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/12043 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/014 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.
摘要翻译：集成电路（IC）封装包括设置在IC封装的第一表面处的电触点，实现电信令接口的集成电路以及可在IC封装的第二表面处接近的连接器组件。连接器组件将机械地连接到另一个连接器组件，并且包括电耦合到电信令接口的接触端子。连接器组件可以被配置为提供与另一连接器组件的摩擦联接，以允许另一连接器组件可移除地附接。一种系统包括IC封装和具有机械连接到IC封装的连接器组件的连接器组件的外部收发器模块。电信令接口根据一种信号格式与外部收发器模块进行信号通信，而外部收发器模块根据另一信号格式通过传输介质进行信令传输。

8. 发明申请

US20100171547A1 PSEUDO BANDGAP VOLTAGE REFERENCE CIRCUIT 审中-公开
标题翻译： PSEUDO带隙电压参考电路
公开(公告)号：US20100171547A1
公开(公告)日：2010-07-08
申请号：US12349810
申请日：2009-01-07
申请人： Emerson S. Fang , Tin Tin Wee , Sanjeev K. Maheshwari
发明人： Emerson S. Fang , Tin Tin Wee , Sanjeev K. Maheshwari
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A pseudo bandgap voltage reference circuit includes a first transistor and a second transistor, each coupled to a supply voltage node. The circuit also includes an amplifier circuit coupled to a gate terminal of each of the first and the second transistors, a current source coupled to the supply voltage node, and a first diode coupled between the current source and a ground reference node. A first input of the amplifier circuit is coupled to a node between the current source and the first diode. In addition, a first terminal of the first transistor is coupled to a second input of the amplifier circuit in a feedback loop. Also, an output reference voltage is developed at an output node coupled to a second terminal of the second transistor. Further, an output current of the current source is independent of a current flowing through the first terminal of the first transistor.
摘要翻译：伪带隙电压参考电路包括第一晶体管和第二晶体管，每个耦合到电源电压节点。电路还包括耦合到第一和第二晶体管中的每一个的栅极端子的放大器电路，耦合到电源电压节点的电流源以及耦合在电流源和接地参考节点之间的第一二极管。放大器电路的第一输入耦合到电流源和第一二极管之间的节点。此外，第一晶体管的第一端子在反馈环路中耦合到放大器电路的第二输入端。此外，在耦合到第二晶体管的第二端子的输出节点处产生输出参考电压。此外，电流源的输出电流与流过第一晶体管的第一端子的电流无关。

9. 发明授权

US06577305B1 Apparatus and method for performing setup operations in a 3-D graphics pipeline using unified primitive descriptors 有权
标题翻译：用于使用统一原语描述符在3-D图形管线中执行设置操作的装置和方法
公开(公告)号：US06577305B1
公开(公告)日：2003-06-10
申请号：US09378598
申请日：1999-08-20
申请人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Hengwei Hsu , Sushma S. Trivedi
发明人： Jerome F. Duluk, Jr. , Richard E. Hessel , Vaughn T. Arnold , Jack Benkual , George Cuan , Stephen L. Dodgen , Emerson S. Fang , Hengwei Hsu , Sushma S. Trivedi
IPC分类号： G06T1700
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： The present invention provides post tile sorting setup in a tiled graphics pipeline architecture. In particular, the present invention determines a set of clipping points that identify intersections of a primitive with a tile. The mid-pipeline setup unit is adapted to compute a minimum depth value for that part of the primitive intersecting the tile. The mid-pipeline setup unit can be adapted to process primitives with x-coordinates that are screen based and y-coordinates that are tile based. Additionally, to the mid-pipeline setup unit is adapted to represent both line segments and triangles as quadrilaterals, wherein not all of a quadrilateral's vertices are required to describe a triangle.
摘要翻译：本发明提供了一种平铺图形流水线架构中的贴砖排序设置。特别地，本发明确定了识别原始图像与瓦片的交叉点的一组剪切点。中间管道设置单元适于计算与瓦片相交的原始部分的最小深度值。中间流水线设置单元可以适用于处理基于屏幕的x坐标的基元和基于瓦片的y坐标。另外，中间流水线设置单元适于将线段和三角形表示为四边形，其中不需要全部四边形的顶点来描述三角形。

10. 发明授权

US08729944B2 Clock generator with integrated phase offset programmability 有权
标题翻译：具有集成相位偏移可编程性的时钟发生器
公开(公告)号：US08729944B2
公开(公告)日：2014-05-20
申请号：US13333011
申请日：2011-12-21
申请人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
发明人： Bruce A. Doyle , Emerson S. Fang , Alvin L. Loke , Shawn Searles , Stephen F. Greenwood
IPC分类号： H03K5/13
CPC分类号： H03K3/0322 , H03L7/0996
摘要： A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.
摘要翻译：装置可以包括第一，第二和第三缓冲级。该装置还可以包括选择器电路，用于选择性地输出第二缓冲级的输出或第三缓冲级的输出之一。器件可以包括输出以提供第一时钟信号，其中第一时钟信号是第一缓冲器级的输出，并且器件还包括输出以提供第二时钟信号，其中第二时钟信号是选择器电路。

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