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1. 发明授权

US07685487B1 Simultaneous core testing in multi-core integrated circuits 有权
标题翻译：多核心集成电路同时核心测试
公开(公告)号：US07685487B1
公开(公告)日：2010-03-23
申请号：US11086924
申请日：2005-03-22
申请人： Ting-Yu Kuo , Dwight K. Elvey
发明人： Ting-Yu Kuo , Dwight K. Elvey
IPC分类号： G01R31/28
CPC分类号： G01R31/318563
摘要： Various embodiments of methods and systems for simultaneously testing multiple cores included in an integrated circuit are disclosed. In one embodiment, an integrated circuit may include two or more logic cores. The IC may also include structural scan test hardware coupled to the cores. This structural scan test hardware may be capable of inputting scan test vector data into scan registers associated with each of the logic cores, simultaneously executing a scan test on the logic cores included in the IC, and outputting the results of the scan tests for multiple cores to automated test equipment (ATE) simultaneously. In one embodiment, elements of the results of testing for multiple cores may be interleaved on a single output line such that an element of test result data from each core is present on an input channel to the ATE during each strobe window.
摘要翻译：公开了用于同时测试集成电路中包括的多个核的方法和系统的各种实施例。在一个实施例中，集成电路可以包括两个或更多个逻辑核。 IC还可以包括耦合到核的结构扫描测试硬件。该结构扫描测试硬件可能能够将扫描测试矢量数据输入到与每个逻辑核心相关联的扫描寄存器中，同时对包含在IC中的逻辑核心执行扫描测试，并输出多个核心的扫描测试结果同时进行自动化测试设备（ATE）。在一个实施例中，用于多个核心的测试结果的元素可以交织在单个输出线上，使得来自每个核心的测试结果数据的元素在每个选通窗口期间的输入信道上存在于ATE。

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