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1. 发明授权

US5405801A Method for manufacturing a capacitor of a semiconductor device 失效
标题翻译：半导体装置的电容器的制造方法
公开(公告)号：US5405801A
公开(公告)日：1995-04-11
申请号：US25421
申请日：1993-03-01
申请人： Ki-man Han , Chang-gyu Hwang , Dug-dong Kang , Young-Jae Choi , Joo-young Yoon
发明人： Ki-man Han , Chang-gyu Hwang , Dug-dong Kang , Young-Jae Choi , Joo-young Yoon
IPC分类号： H01L27/04 , H01L21/02 , H01L21/3213 , H01L21/3215 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L21/32134 , H01L21/32139 , H01L21/32155 , H01L27/10808 , H01L28/84 , H01L29/66181 , H01L28/86 , H01L28/90 , Y10S148/016 , Y10S148/138
摘要： A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.
摘要翻译：公开了一种用于制造半导体器件的电容器的第一电极的方法。在形成由具有微观结构的晶粒构成的多晶层，在其中含有杂质的情况下，蚀刻多晶层以切割晶粒的边界部分，从而使多晶层的表面变得坚固。通过在暴露第一坚固多晶层的表面之后使用氧化物层或各向异性蚀刻形成微沟槽或微柱，并且通过外延生长形成外延晶粒，从而可以进一步增加电池电容。简单的过程允许形成具有规则性和再现性的可靠的半导体器件，并且能够容易地增加和调整电池电容。

2. 发明授权

US6080613A Methods of forming integrated circuit memory devices having improved bit line and storage electrode contact regions therein 失效
标题翻译：形成其中具有改进的位线和存储电极接触区域的集成电路存储器件的方法
公开(公告)号：US6080613A
公开(公告)日：2000-06-27
申请号：US764202
申请日：1996-12-13
申请人： Young-woo Seo , Dug-dong Kang , Sun-cheol Hong , Won-cheol Hong
发明人： Young-woo Seo , Dug-dong Kang , Sun-cheol Hong , Won-cheol Hong
IPC分类号： H01L21/265 , H01L21/8242 , H01L27/108 , H01L21/8234
CPC分类号： H01L27/10873 , H01L27/10808
摘要： Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of simultaneously forming storage electrode and bit line contact regions of first conductivity type in a semiconductor region of second conductivity type. The contact regions preferably receive a double dose of first conductivity type dopants. This double dose compensates for etching damage caused during processing and improves the memory cell's refresh characteristics. The preferred methods of forming DRAM memory cells include the steps of forming an electrically insulating layer on a face of a semiconductor substrate containing a region of second conductivity type therein (e.g., P-type) extending to the face, and then forming a word line (or segment thereof) on the electrically insulating layer, opposite the region of second conductivity type. Contact regions of first conductivity type for a storage electrode and bit line are then formed at the same time at adjacent opposing edges of the word lines by implanting dopants of first conductivity type into the region of second conductivity type using the word line as an implant mask. A storage electrode of a capacitor is then formed on (or coupled to) the storage electrode contact region adjacent a first edge of the word line and a bit line is also preferably formed on (or coupled to) the bit line contact region adjacent a second edge of the word line. The bit line contact region and storage electrode contact region preferably receive a double dose of first conductivity type dopants by performing a first ion implant step, forming sidewall spacers on the first and second edges of the word line and then performing a second ion implant step using the sidewall spacers as an implant mask.
摘要翻译：形成诸如DRAM存储单元的集成电路存储器件的方法包括在第二导电类型的半导体区域中同时形成第一导电类型的存储电极和位线接触区的步骤。接触区优选地接收双剂量的第一导电类型的掺杂剂。该双剂量补偿了在处理过程中造成的蚀刻损伤，并提高了存储单元的刷新特性。形成DRAM存储单元的优选方法包括以下步骤：在包含延伸到面部的第二导电类型区域（例如，P型）的半导体衬底的表面上形成电绝缘层，然后形成字线（或其片段）在与第二导电类型的区域相反的电绝缘层上。然后通过将第一导电类型的掺杂剂注入到第二导电类型的区域中，使用字线作为植入掩模，在相邻的字线的相对边缘处同时形成用于存储电极和位线的第一导电类型的接触区域。然后，在与字线的第一边缘相邻的存储电极接触区域上形成电容器的存储电极（或耦合到）存储电极接触区域，并且位线也优选地形成在邻近第二个位线的位线接触区域（或耦合到）位线接触区域字线的边缘。位线接触区域和存储电极接触区域优选地通过执行第一离子注入步骤接收双剂量的第一导电类型掺杂剂，在字线的第一和第二边缘上形成侧壁间隔物，然后使用侧壁间隔件作为植入物掩模。

3. 发明授权

US5930621A Methods for forming vertical electrode structures and related structures 失效
标题翻译：形成垂直电极结构和相关结构的方法
公开(公告)号：US5930621A
公开(公告)日：1999-07-27
申请号：US806065
申请日：1997-02-25
申请人： Dug-Dong Kang , Yun-seung Shin
发明人： Dug-Dong Kang , Yun-seung Shin
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for forming an electrode for an integrated circuit device includes the steps of forming a first conductive layer on a surface of a microelectronic substrate, and forming a patterned photoresist layer on the first conductive layer. A spacer is formed along sidewalls of the patterned photoresist layer, and the first conductive layer is etched to a predetermined depth less than a thickness of the first conductive layer using the patterned photoresist layer and the spacer as an etch mask thereby defining a hole in the first conductive layer. A protective layer is formed in the hole which covers exposed portions of the first conductive layer, and the patterned photoresist layer is removed. The first conductive layer is then etched using the spacer and the protective layer as an etching mask to form a vertical electrode structure. Related structures are also discussed.
摘要翻译：一种形成集成电路器件电极的方法包括以下步骤：在微电子衬底的表面上形成第一导电层，并在第一导电层上形成图案化的光致抗蚀剂层。沿图案化的光致抗蚀剂层的侧壁形成间隔物，并且使用图案化的光致抗蚀剂层和间隔物作为蚀刻掩模，将第一导电层蚀刻到小于第一导电层的厚度的预定深度，从而在第一导电层。在该孔中形成保护层，其覆盖第一导电层的暴露部分，并去除图案化的光致抗蚀剂层。然后使用间隔物和保护层作为蚀刻掩模蚀刻第一导电层以形成垂直电极结构。还讨论了相关结构。

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