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1. 发明授权

US5405801A Method for manufacturing a capacitor of a semiconductor device 失效
标题翻译：半导体装置的电容器的制造方法
公开(公告)号：US5405801A
公开(公告)日：1995-04-11
申请号：US25421
申请日：1993-03-01
申请人： Ki-man Han , Chang-gyu Hwang , Dug-dong Kang , Young-Jae Choi , Joo-young Yoon
发明人： Ki-man Han , Chang-gyu Hwang , Dug-dong Kang , Young-Jae Choi , Joo-young Yoon
IPC分类号： H01L27/04 , H01L21/02 , H01L21/3213 , H01L21/3215 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L21/32134 , H01L21/32139 , H01L21/32155 , H01L27/10808 , H01L28/84 , H01L29/66181 , H01L28/86 , H01L28/90 , Y10S148/016 , Y10S148/138
摘要： A method for manufacturing first electrode of a capacitor of a semiconductor device is disclosed. After forming a polycrystalline layer composed of grains with microscopic structure to include an impurity in them, the polycrystalline layer is etched to cut the boundary portions of the grains, thereby allowing the surface of the polycrystalline layer to be rugged. The micro-trenches or micro-pillars are formed by using the oxide layer or an anisotropic etching after exposing the surface of the first rugged polycrystalline layer, and epitaxial grains are formed by epitaxial growth, so that cell capacitance can be further increased. The simple process allows the formation of a reliable semiconductor device having regularity and reproducibility, and capable of increasing and adjusting the cell capacitance easily.
摘要翻译：公开了一种用于制造半导体器件的电容器的第一电极的方法。在形成由具有微观结构的晶粒构成的多晶层，在其中含有杂质的情况下，蚀刻多晶层以切割晶粒的边界部分，从而使多晶层的表面变得坚固。通过在暴露第一坚固多晶层的表面之后使用氧化物层或各向异性蚀刻形成微沟槽或微柱，并且通过外延生长形成外延晶粒，从而可以进一步增加电池电容。简单的过程允许形成具有规则性和再现性的可靠的半导体器件，并且能够容易地增加和调整电池电容。

2. 发明授权

US5358893A Isolation method for semiconductor device 失效
标题翻译：半导体器件的隔离方法
公开(公告)号：US5358893A
公开(公告)日：1994-10-25
申请号：US118818
申请日：1993-09-10
申请人： Won-suk Yang , Min-uk Hwang , Chang-gyu Hwang
发明人： Won-suk Yang , Min-uk Hwang , Chang-gyu Hwang
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76216 , H01L21/32 , Y10S148/117
摘要： An improved isolation method in a semiconductor device of selective polysilicon oxidation (SEPOX) which can create a field oxide layer having a size below the optical resolution and good isolation characteristics. A buffer layer comprised of polysilicon or amorphous silicon is formed on a semiconductor substrate, and then an anti-oxidative pattern with an opening which defines an isolation region exposing a portion of the buffer layer is formed. Then a portion of the exposed buffer layer is isotropically etched in order to form an undercut portion in the lower portion around the opening. Then an anti-oxidative spacer filling the undercut portion is formed on the sidewall of the opening. Thereafter, a field oxide layer is formed by partially oxidizing the portion of the buffer layer exposed by the opening and the semiconductor substrate exposed in the opening. The size of bird's beak is decreased, thereby forming a field oxide layer with good isolation characteristics and small size.
摘要翻译：在选择性多晶硅氧化（SEPOX）的半导体器件中的改进的隔离方法，其可以产生尺寸低于光学分辨率和良好隔离特性的场氧化物层。在半导体衬底上形成由多晶硅或非晶硅组成的缓冲层，然后形成具有限定了缓冲层的一部分的隔离区的开口的抗氧化图案。然后，暴露的缓冲层的一部分被各向同性蚀刻，以便在开口周围的下部形成底切部分。然后在开口的侧壁上形成填充底切部分的抗氧化间隔物。此后，通过部分氧化由开口暴露的缓冲层的部分和暴露在开口中的半导体衬底而形成场氧化物层。鸟喙的尺寸减小，形成具有良好隔离特性和小尺寸的场氧化物层。

3. 发明授权

US5858833A Methods for manufacturing integrated circuit memory devices including trench buried bit lines 失效
标题翻译：包括沟槽埋置位线的集成电路存储器件的制造方法
公开(公告)号：US5858833A
公开(公告)日：1999-01-12
申请号：US781374
申请日：1997-01-21
申请人： Won-seong Lee , Chang-gyu Hwang
发明人： Won-seong Lee , Chang-gyu Hwang
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808
摘要： Integrated circuit memory devices are manufactured by forming spaced apart source and drain regions in an integrated circuit substrate, and an insulated gate on the integrated circuit substrate therebetween. An interlayer insulating layer is formed on the integrated circuit substrate, including first and second conductive pad contacts which extend therethrough and which electrically contact the source and the drain region, respectively. A trench is formed in the interlayer insulating layer, including in the second conductive pad contact. A first insulating layer is formed to line the trench, except for adjacent the second conductive pad contact. A buried bit line is formed in the trench, electrically contacting the second conductive pad contact through the first insulating layer. A second insulating layer is formed on the first insulating layer and on the buried bit line, except for adjacent the first conductive pad contact. A patterned storage electrode is formed on the second insulating layer, which electrically contacts the first conductive contact pad.
摘要翻译：通过在集成电路基板中形成间隔开的源极和漏极区域以及集成电路存储器件之间的集成电路基板上的绝缘栅极来制造集成电路存储器件。在集成电路基板上形成层间绝缘层，其中包括分别延伸通过其并与源区和漏区电接触的第一和第二导电焊盘触点。沟槽形成在层间绝缘层中，包括在第二导电焊盘触点中。除了与第二导电焊盘接触件相邻之外，形成第一绝缘层以排列沟槽。在沟槽中形成掩埋位线，使第二导电焊盘触点与第一绝缘层电接触。第二绝缘层形成在第一绝缘层和掩埋位线上，除了与第一导电焊盘接触相邻。图案化的存储电极形成在与第一导电接触焊盘电接触的第二绝缘层上。

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