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1. 发明授权

US5119480A Bus master interface circuit with transparent preemption of a data transfer operation 失效
标题翻译：具有数据传输操作透明度预警的总线主接口电路
公开(公告)号：US5119480A
公开(公告)日：1992-06-02
申请号：US434385
申请日：1989-11-13
申请人： Serafin J. E. Garcia, Jr. , Douglas R. Chisholm , Dean A. Kalman , Russell S. Padgett , Robert D. Yoder
发明人： Serafin J. E. Garcia, Jr. , Douglas R. Chisholm , Dean A. Kalman , Russell S. Padgett , Robert D. Yoder
IPC分类号： G06F13/32 , G06F13/362
CPC分类号： G06F13/32
摘要： A plurality of specialized controllers (e.g., 202, 204 & 206), each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus (104) and a local bus (106) on a computer adapter card (102). When the Direct Memory Access (DMA) controller (202) is controlling a DMA operation on the local bus, certain other controllers (204 & 206) can break-in to the current DMA operation, temporarily halting the DMA opertion until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit (212) are temporarily blocked by blocking signals from a break-in logic circuit (210). The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

2. 发明授权

US5003465A Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device 失效
标题翻译：用于在公共存储器和输入/输出装置之间的DMA读/写操作期间通过输入/输出总线增加系统吞吐量并提高计算机系统的地址能力的方法和装置
公开(公告)号：US5003465A
公开(公告)日：1991-03-26
申请号：US212292
申请日：1988-06-27
申请人： Douglas R. Chisholm , Robert G. Iseminger , Richard A. Kelley , Wan L. Leung , James T. Moyer , Mark C. Snedaker
发明人： Douglas R. Chisholm , Robert G. Iseminger , Richard A. Kelley , Wan L. Leung , James T. Moyer , Mark C. Snedaker
IPC分类号： G06F13/36 , G06F13/28
CPC分类号： G06F13/28
摘要： In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of "storage latency" that occur after a DMA storage operation has been initiated by one IOP.

3. 发明授权

US5455916A Method for performing inter-unit data transfer operations among a plurality of input/output bus interface units coupled to a common asynchronous bus 失效
标题翻译：用于在耦合到公共异步总线的多个输入/输出总线接口单元之间执行单元间数据传送操作的方法
公开(公告)号：US5455916A
公开(公告)日：1995-10-03
申请号：US371041
申请日：1995-01-10
申请人： Donall G. Bourke , Douglas R. Chisholm , Gregory D. Float , Richard A. Kelley , Roy Y. Liu , Carl A. Malmquist , John M. Nelson , Charles B. Perkins, Jr. , Richard L. Place , Hartmut R. Schwermer , John D. Wilson
发明人： Donall G. Bourke , Douglas R. Chisholm , Gregory D. Float , Richard A. Kelley , Roy Y. Liu , Carl A. Malmquist , John M. Nelson , Charles B. Perkins, Jr. , Richard L. Place , Hartmut R. Schwermer , John D. Wilson
IPC分类号： G06F13/36 , G06F13/40 , G06F13/38 , G06F13/42
CPC分类号： G06F13/405
摘要： In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.
摘要翻译：在数据处理系统中，输入输出总线单元（IOBU）通过异步总线连接到输入输出接口控制器（IOIC）的一端。 IOIC的另一端通过同步总线连接到存储控制器（SC）和输入输出接口单元（IOIU）。 SC和IOIU连接到存储器单元和指令处理单元。由三个子总线和控制总线组成的异步总线以异步“握手”的方式在IOIC和IOBU之间传输信号。由两个子总线和控制总线组成的同步总线以同步方式在IOIC和SC / IOIU之间传输信号。在同步总线和异步总线之间互连的IOIC作为较快的同步总线和较慢的异步总线之间的缓冲器。通过异步总线，IOIC，同步总线和SC / IOIU在IOBU和存储器单元之间执行各种操作，例如单元操作，存储操作和消息接受操作。

4. 发明授权

US5276814A Method for transferring information between main store and input output bus units via a sequence of asynchronous bus and two synchronous buses 失效
标题翻译：用于通过异步总线和两个同步总线的序列在主存储和输入总线单元之间传送信息的方法
公开(公告)号：US5276814A
公开(公告)日：1994-01-04
申请号：US351181
申请日：1989-05-10
申请人： Donall G. Bourke , Douglas R. Chisholm , Gregory D. Float , Richard A. Kelley , Roy Y. Liu , Carl A. Malmquist , John M. Nelson , Charles B. Perkins, Jr. , Richard L. Place , Hartmut R. Schwermer , John D. Wilson
发明人： Donall G. Bourke , Douglas R. Chisholm , Gregory D. Float , Richard A. Kelley , Roy Y. Liu , Carl A. Malmquist , John M. Nelson , Charles B. Perkins, Jr. , Richard L. Place , Hartmut R. Schwermer , John D. Wilson
IPC分类号： G06F13/36 , G06F13/40 , G06F13/38 , G06F13/10
CPC分类号： G06F13/405
摘要： In a data processing system, an input output bus unit (IOBU) is connected one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous handshaking manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, message acceptance operation.
摘要翻译：在数据处理系统中，输入输出总线单元（IOBU）通过异步总线连接在输入输出接口控制器（IOIC）的一端。 IOIC的另一端通过同步总线连接到存储控制器（SC）和输入输出接口单元（IOIU）。 SC和IOIU连接到存储器单元和指令处理单元。由三个子总线和控制总线组成的异步总线以异步握手的方式在IOIC和IOBU之间进行信号传输。由两个子总线和控制总线组成的同步总线以同步方式在IOIC和SC / IOIU之间传输信号。在同步总线和异步总线之间互连的IOIC作为较快的同步总线和较慢的异步总线之间的缓冲器。通过异步总线，IOIC，同步总线，消息接收操作在IOBU和存储器单元之间执行各种操作。

5. 发明授权

US4373181A Dynamic device address assignment mechanism for a data processing system 失效
标题翻译：用于数据处理系统的动态设备地址分配机制
公开(公告)号：US4373181A
公开(公告)日：1983-02-08
申请号：US173586
申请日：1980-07-30
申请人： Douglas R. Chisholm , Hobart L. Kurtz, Jr.
发明人： Douglas R. Chisholm , Hobart L. Kurtz, Jr.
IPC分类号： G06F13/14 , G06F12/02 , G06F12/06 , G06F9/30
CPC分类号： G06F12/0661
摘要： A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.
摘要翻译：描述了外围设备地址分配机制，其不需要使用插板或跳线。该机制使得主机处理器能够在任何期望的时间选择任何所需的外围设备并将其设备地址设置为任何所需的值。这通过为每个外围设备控制单元提供一个可装载的设备地址寄存器来实现，用于保持分配给其外围设备的设备地址。每个设备控制单元还提供有响应于在处理器I / O总线上出现唯一I / O命令的电路以及由处理器激活一组唯一I / O总线数据线，以将其加载到其中设备地址通过I / O总线注册处理器提供的所需设备地址值。

6. 发明授权

US5509124A Coupled synchronous-asychronous bus structure for transferring data between a plurality of peripheral input/output controllers and a main data store 失效
标题翻译：用于在多个外围输入/输出控制器和主数据存储器之间传送数据的耦合同步同步总线结构
公开(公告)号：US5509124A
公开(公告)日：1996-04-16
申请号：US486160
申请日：1995-06-07
申请人： Donall G. Bourke , Douglas R. Chisholm , Gregory D. Float , Richard A. Kelley , Roy Y. Liu , Carl A. Malmquist , John M. Nelson , Charles B. Perkins, Jr. , Richard L. Place , Hartmut R. Schwermer , John D. Wilson
发明人： Donall G. Bourke , Douglas R. Chisholm , Gregory D. Float , Richard A. Kelley , Roy Y. Liu , Carl A. Malmquist , John M. Nelson , Charles B. Perkins, Jr. , Richard L. Place , Hartmut R. Schwermer , John D. Wilson
IPC分类号： G06F13/36 , G06F13/40 , G06F13/38
CPC分类号： G06F13/405
摘要： In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.
摘要翻译：在数据处理系统中，输入输出总线单元（IOBU）通过异步总线连接到输入输出接口控制器（IOIC）的一端。 IOIC的另一端通过同步总线连接到存储控制器（SC）和输入输出接口单元（IOIU）。 SC和IOIU连接到存储器单元和指令处理单元。由三个子总线和控制总线组成的异步总线以异步“握手”的方式在IOIC和IOBU之间传输信号。由两个子总线和控制总线组成的同步总线以同步方式在IOIC和SC / IOIU之间传输信号。在同步总线和异步总线之间互连的IOIC作为较快的同步总线和较慢的异步总线之间的缓冲器。通过异步总线，IOIC，同步总线和SC / IOIU在IOBU和存储器单元之间执行各种操作，例如单元操作，存储操作和消息接受操作。

7. 发明授权

US5199106A Input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the bus 失效
标题翻译：将同步总线连接到异步总线的输入输出接口控制器以及在总线上执行操作的方法
公开(公告)号：US5199106A
公开(公告)日：1993-03-30
申请号：US568530
申请日：1990-08-15
申请人： Donall G. Bourke , Douglas R. Chisholm , Gregory D. Float , Richard A. Kelley , Roy Y. Liu , Carl A. Malmquist , John M. Nelson , Charles B. Perkins, Jr. , Richard L. Place , Hartmut R. Schwermer , John D. Wilson
发明人： Donall G. Bourke , Douglas R. Chisholm , Gregory D. Float , Richard A. Kelley , Roy Y. Liu , Carl A. Malmquist , John M. Nelson , Charles B. Perkins, Jr. , Richard L. Place , Hartmut R. Schwermer , John D. Wilson
IPC分类号： G06F13/40
CPC分类号： G06F13/405
摘要： In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.
摘要翻译：在数据处理系统中，输入输出总线单元（IOBU）通过异步总线连接到输入输出接口控制器（IOIC）的一端。 IOIC的另一端通过同步总线连接到存储控制器（SC）和输入输出接口单元（IOIU）。 SC和IOIU连接到存储器单元和指令处理单元。由三个子总线和控制总线组成的异步总线以异步“握手”的方式在IOIC和IOBU之间传输信号。由两个子总线和控制总线组成的同步总线以同步方式在IOIC和SC / IOIU之间传输信号。在同步总线和异步总线之间互连的IOIC作为较快的同步总线和较慢的异步总线之间的缓冲器。通过异步总线，IOIC，同步总线和SC / IOIU在IOBU和存储器单元之间执行各种操作，例如单元操作，存储操作和消息接受操作。

8. 发明授权

US5131082A Command delivery for a computing system for transfers between a host and subsystem including providing direct commands or indirect commands indicating the address of the subsystem control block 失效
标题翻译：用于主机和子系统之间转移的计算系统的指令传递，包括提供指示子系统控制块的地址的提供的直接命令或间接命令
公开(公告)号：US5131082A
公开(公告)日：1992-07-14
申请号：US364931
申请日：1989-06-09
申请人： Francis M. Bonevento , Douglas R. Chisholm , Sammy D. Dodds , Dhruvkumar M. Desai , Ernest N. Mandese , Andrew B. McNeill , Richard N. Mendelson
发明人： Francis M. Bonevento , Douglas R. Chisholm , Sammy D. Dodds , Dhruvkumar M. Desai , Ernest N. Mandese , Andrew B. McNeill , Richard N. Mendelson
IPC分类号： G06F13/12
CPC分类号： G06F13/126
摘要： A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

9. 发明授权

US5014186A Data-processing system having a packet transfer type input/output system 失效
标题翻译：数据处理系统具有分组传送型输入/输出系统
公开(公告)号：US5014186A
公开(公告)日：1991-05-07
申请号：US250996
申请日：1988-09-27
申请人： Douglas R. Chisholm
发明人： Douglas R. Chisholm
IPC分类号： G06F13/28 , G06F13/38 , G06F13/40
CPC分类号： G06F13/4018 , G06F13/28 , G06F13/385
摘要： In a data processing system having a system bus for coupling I/O units to a system storage unit, there is provided a mechanism for supplying to the I/O units a line size signal representing the line size of the system storage unit. A further mechanism is located in at least one of the I/O units for responding to this line size signal for adjusting the data transfer size of the I/O unit to match the system storage unit line size.
摘要翻译：在具有用于将I / O单元耦合到系统存储单元的系统总线的数据处理系统中，提供了一种用于向I / O单元提供表示系统存储单元的行大小的行尺寸信号的机构。另外的机构位于至少一个I / O单元中，用于响应于该线路尺寸信号，用于调整I / O单元的数据传输大小以匹配系统存储单元线路尺寸。

10. 发明授权

US4246637A Data processor input/output controller 失效
标题翻译：数据处理器输入/输出控制器
公开(公告)号：US4246637A
公开(公告)日：1981-01-20
申请号：US919107
申请日：1978-06-26
申请人： Lewis W. Brown , Douglas R. Chisholm , Jerry D. Dixon
发明人： Lewis W. Brown , Douglas R. Chisholm , Jerry D. Dixon
IPC分类号： G06F13/12 , G06F13/32 , G06F3/00 , G06F9/22 , G06F15/16
CPC分类号： G06F13/32
摘要： A data processor input/output controller which is particularly useful as a microcontroller for the transfer of data between a host processor and one or more peripheral input/output devices in a digital data processing system. This input/output (I/O) controller is a subchannel controller for offloading a goodly portion of the subchannel control function from the host processor. This I/O controller includes a microprocessor for assisting and supervising the controller internal operations. Also included in the controller is an automatic high-speed data bypass mechanism whereby data may be transferred from the host processor to the I/O device or vice versa without having to pass through the microprocessor and without requiring any intervention on the part of the microprocessor during such automatic transfer. Provision is made for enabling the microprocessor to perform other functions, such as the presentation of interrupts to the host processor and the servicing of additional I/O commands from the host processor concurrently with the transfer of data via the automatic bypass mechanism. This capability is particularly useful where two or more I/O devices are connected to the controller. The automatic bypass mechanism is constructed to communicate with the host processor in a cycle steal mode. A look-ahead mechanism is provided for more quickly issuing the cycle steal requests to the host processor when operating in the automatic bypass mode.
摘要翻译：一种数据处理器输入/输出控制器，其特别用作用于在主处理器与数字数据处理系统中的一个或多个外围输入/输出设备之间传送数据的微控制器。该输入/输出（I / O）控制器是用于从主处理器卸载子通道控制功能的很好部分的子通道控制器。该I / O控制器包括用于辅助和监督控制器内部操作的微处理器。还包括在控制器中的是一种自动高速数据旁路机制，其中数据可以从主机处理器传送到I / O设备，反之亦然，而不必通过微处理器而不需要微处理器的任何干预在这种自动转移过程中。提供了使微处理器能够执行其他功能，例如向主机处理器呈现中断，以及通过自动旁路机制与主机处理器同时传送数据的附加I / O命令的服务。当两个或多个I / O设备连接到控制器时，此功能特别有用。自动旁路机构被构造成以循环窃取模式与主机处理器进行通信。提供了一种提前机制，用于在以自动旁路模式操作时更快地向主机处理器发出周期窃取请求。

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