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1. 发明授权

US06477603B1 Multiple PCI adapters within single PCI slot on an matax planar 失效
标题翻译：单个PCI插槽中的多个PCI适配器
公开(公告)号：US06477603B1
公开(公告)日：2002-11-05
申请号：US09358106
申请日：1999-07-21
申请人： Howard J. Locker , Daryl C. Cromer , Ernest N. Mandese , James Peter Ward , John K. Langgood , Joseph Pennisi , Jan M. Janick
发明人： Howard J. Locker , Daryl C. Cromer , Ernest N. Mandese , James Peter Ward , John K. Langgood , Joseph Pennisi , Jan M. Janick
IPC分类号： G06F1300
CPC分类号： G06F13/409 , H05K1/14
摘要： Multiple PCI adapter cards are supported by a single PCI slot through the aspects of the present invention. A computer system aspect includes an &mgr;ATX planar including at least one PCI slot, and a riser card mounted in the at least one PCI slot, the riser card supporting multiple PCI adapter cards and providing signal generation to allow the multiple PCI adapter cards to utilize the at least one PCI slot. The riser card aspect includes a PCI connector for coupling to a PCI slot on the &mgr;ATX planar, a plurality of PCI slots for attaching a plurality of PCI adapter cards, and a logic device for providing separate bus signal pairs to each of the plurality of PCI adapter cards from a single signal pair of the PCI slot on the &mgr;ATX planar.
摘要翻译：通过本发明的方面，单个PCI插槽支持多个PCI适配器卡。计算机系统方面包括包括至少一个PCI插槽的muATX平面和安装在所述至少一个PCI插槽中的转接卡，所述转接卡支持多个PCI适配器卡并提供信号产生以允许所述多个PCI适配器卡利用至少一个PCI插槽。提升卡方面包括用于耦合到muATX平面上的PCI插槽的PCI连接器，用于附接多个PCI适配器卡的多个PCI插槽，以及用于向多个PCI中的每一个提供单独的总线信号对的逻辑设备来自单个信号对的适配器卡在muATX平面上的PCI插槽。

2. 发明授权

US5265255A Personal computer system with interrupt controller 失效
标题翻译：带中断控制器的个人计算机系统
公开(公告)号：US5265255A
公开(公告)日：1993-11-23
申请号：US586662
申请日：1990-09-24
申请人： Francis M. Bonevento , Ernest N. Mandese , Richard N. Mendelson
发明人： Francis M. Bonevento , Ernest N. Mandese , Richard N. Mendelson
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： This disclosure relates to personal computer systems, and more particularly to a personal computer which provides for interrupt redirection of the activity of a microprocessor. The personal computer system has a multichannel bus for transferring data, a microprocessor for manipulating data and coupled to the bus, and a plurality of input/output devices coupled to the bus for receiving and delivering data for manipulation by the microprocessor. Each input/output device is capable of generating a logical interrupt signal indicative of a request for access to the microprocessor and of being remotely reset to a non-interrupt condition, and all of the devices deliver their logical interrupt signals through a common physical channel of the bus. An interrupt controller is coupled to the microprocessor and bus for recognizing delivery of an interrupt signal and for periodically generating an interrupt reset signal and delivering reset signals to all of the input/output devices simultaneously for setting all of the devices to a condition indicative of no request for access to said microprocessor.

3. 发明授权

US5481724A Peer to peer computer-interrupt handling 失效
标题翻译：对等计算机中断处理
公开(公告)号：US5481724A
公开(公告)日：1996-01-02
申请号：US43331
申请日：1993-04-06
申请人： Arthur J. Heimsoth , Ernest N. Mandese , Joseph P. McGovern , Richard N. Mendelson
发明人： Arthur J. Heimsoth , Ernest N. Mandese , Joseph P. McGovern , Richard N. Mendelson
IPC分类号： G06F13/24 , G06F13/00
CPC分类号： G06F13/24
摘要： A coded logical interrupt signal is sent between system or subsystem units in a data processing system. The logical interrupt is sent by a sending unit, that requests the interrupt, and is sent to a receiving unit that the sending unit wishes to interrupt. These coded logical interrupts are accumulated in the receiving unit. When the receiving unit is actually physically interrupted by control of the processor in the unit, all logical interrupts that have been accumulated are processed. The logical interrupt may be coded to indicate sending unit, that is the source of the interrupt, and the action being requested by the sending unit. If the interrupt includes only source information, the action information is sent separately by the sending unit to memory in the receiving unit. If the interrupt includes both source identification and action information, the receiving unit can interpret source and action directly from the interrupt.
摘要翻译：在数据处理系统中的系统或子系统单元之间发送编码的逻辑中断信号。逻辑中断由请求中断的发送单元发送，并发送给发送单元希望中断的接收单元。这些编码的逻辑中断被累积在接收单元中。当接收单元实际上通过本机中的处理器的控制被物理中断时，处理已经累积的所有逻辑中断。逻辑中断可以被编码以指示发送单元，即中断的源，以及由发送单元请求的动作。如果中断仅包含源信息，则发送单元将动作信息单独发送到接收单元中的存储器。如果中断包括源标识和动作信息，则接收单元可以直接从中断解释源和动作。

4. 发明授权

US5131082A Command delivery for a computing system for transfers between a host and subsystem including providing direct commands or indirect commands indicating the address of the subsystem control block 失效
标题翻译：用于主机和子系统之间转移的计算系统的指令传递，包括提供指示子系统控制块的地址的提供的直接命令或间接命令
公开(公告)号：US5131082A
公开(公告)日：1992-07-14
申请号：US364931
申请日：1989-06-09
申请人： Francis M. Bonevento , Douglas R. Chisholm , Sammy D. Dodds , Dhruvkumar M. Desai , Ernest N. Mandese , Andrew B. McNeill , Richard N. Mendelson
发明人： Francis M. Bonevento , Douglas R. Chisholm , Sammy D. Dodds , Dhruvkumar M. Desai , Ernest N. Mandese , Andrew B. McNeill , Richard N. Mendelson
IPC分类号： G06F13/12
CPC分类号： G06F13/126
摘要： A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

5. 发明授权

US5185864A Interrupt handling for a computing system with logical devices and interrupt reset 失效
标题翻译：具有逻辑设备和中断复位的计算系统的中断处理
公开(公告)号：US5185864A
公开(公告)日：1993-02-09
申请号：US367391
申请日：1989-06-16
申请人： Francis M. Bonevento , Chester A. Heath , Ernest N. Mandese , Richard N. Mendelson
发明人： Francis M. Bonevento , Chester A. Heath , Ernest N. Mandese , Richard N. Mendelson
IPC分类号： G06F9/48 , G06F13/24
CPC分类号： G06F13/24
摘要： A computing system including a host processor and at least one intelligent subsystem having attached devices, has two interrupt ports. The one intelligent subsystem and the attached devices are each viewed as a logical device by the host processor, and each is assigned a device identification number. The host processor provides direct and indirect commands to the logical devices. For direct commands, first physical interrupts are provided to the host processor serially from the logical devices through an Interrupt Status Port. For indirect commands, logical interrupts are stored in predetermined bit positions in a Device Interrupt Indentifier Port (DIIP) in accordance with the device identification numbers. A second single physical interrupt is provided to the host processor as long as there is at least one logical interrupt pending from at least one logical device as the result of an indirect command. The host processor reads the DIIP to determine which logical devices have at least one logical interrupt pending for an indirect command. A plurality of logical interrupts for a single logical device may be cleared with a single reset interrupt command from the host processor.

6. 发明授权

US5170471A Command delivery for a computing system for transferring data between a host and subsystems with busy and reset indication 失效
标题翻译：用于在具有忙和复位指示的主机和子系统之间传送数据的计算系统的命令传递
公开(公告)号：US5170471A
公开(公告)日：1992-12-08
申请号：US818654
申请日：1992-01-06
申请人： Francis M. Bonevento , Douglas R. Chrisholm , Sammy D. Dodds , Dhruvkumar M. Desai , Ernest N. Mandese , Andrew B. McNeill , Richard N. Mendelson
发明人： Francis M. Bonevento , Douglas R. Chrisholm , Sammy D. Dodds , Dhruvkumar M. Desai , Ernest N. Mandese , Andrew B. McNeill , Richard N. Mendelson
IPC分类号： G06F13/12
CPC分类号： G06F13/126
摘要： A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.
摘要翻译：命令接口包括用于在主机处理器和至少一个可能具有连接设备的智能子系统之间传送信息的端口。命令接口端口接收来自主处理器的直接命令或间接命令，哪些命令指示要由一个子系统或连接的设备执行的操作的类型。注意端口接收来自主处理器的代码，其指示在命令接口端口处接收到直接命令或间接命令中的哪一个，并且还指示一个智能子系统或设备将执行哪一个命令。命令忙/状态端口从一个智能子系统接收指示命令接口端口和注意端口是否忙碌的代码，以及一个智能子系统是否接受或拒绝命令。主机处理器可以读取此端口，而无需更改或更新代码。

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