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1. 发明授权

US5428803A Method and apparatus for a unified parallel processing architecture 失效
标题翻译：统一并行处理架构的方法和装置
公开(公告)号：US5428803A
公开(公告)日：1995-06-27
申请号：US912964
申请日：1992-07-10
申请人： Steve S. Chen , Douglas R. Beard , George A. Spix , Edward C. Priest , John M. Wastlick , James M. VanDyke
发明人： Steve S. Chen , Douglas R. Beard , George A. Spix , Edward C. Priest , John M. Wastlick , James M. VanDyke
IPC分类号： G06F9/38 , G06F1/10 , G06F12/06 , G06F13/16 , G06F15/173 , G06F3/60
CPC分类号： G06F13/1657 , G06F1/10 , G06F13/1663 , G06F15/17337 , G06F15/17381
摘要： A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnection of multiple clusters of processors to a create a floating shared memory effectively combines all three type of memory models, pure shared memory, extended shared memory and distributed shared memory, into a unified parallel processing architecture.
摘要翻译：统一的并行处理架构将多个处理器的可扩展数量的集群连接在一起，以创建高性能并行处理计算机系统。多个处理器被分组到四个或更多个物理上可分离的群集中，每个群集具有由该群集中的所有处理器对称地访问的公共群集共享存储器; 然而，只有一些集群是相互关联的。如果与相对存储器延迟和相对数据局部性相关的某些存储器访问条件可以创建有效的共享存储器并行编程环境，则群集相互互连以形成浮动共享存储器。共享存储器模型可以与可以在单个集群的集群共享存储器中执行的程序一起使用，或者在由包括相邻互连的任何集合的集群共享存储器的扩展共享存储器空间中定义的浮动共享存储器中使用集群。分布式存储器模型可以与要在任何非相邻互连的集群的集群共享存储器中执行的任何程序一起使用。处理器的多个集群的相邻互连以创建浮动共享存储器有效地将所有三种类型的存储器模型，纯共享存储器，扩展共享存储器和分布式共享存储器组合成统一的并行处理架构。

2. 发明授权

US5168547A Distributed architecture for input/output for a multiprocessor system 失效
标题翻译：用于多处理器系统的输入/输出的分布式架构
公开(公告)号：US5168547A
公开(公告)日：1992-12-01
申请号：US536182
申请日：1990-06-11
申请人： Edward C. Miller , Steve S. Chen , Frederick J. Simmons , George A. Spix , Leonard S. Veil , Mark J. Vogel , John M. Wastlick
发明人： Edward C. Miller , Steve S. Chen , Frederick J. Simmons , George A. Spix , Leonard S. Veil , Mark J. Vogel , John M. Wastlick
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30087 , G06F9/30094 , G06F9/30098 , G06F9/30101 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A distributed architecture for the input/output system for a multiprocessor system provides for equal and democratic access to all shared hardware resources by both the processors and the external interface ports of the multiprocessor system. This allows one or more input/output concentrators attached to the external interface ports to have complete access to all of the shared hardware resources across the multiprocessor system without requiring processor intervention. The distributed input/output system provides for communication of data and control information between a set of common shared hardware resources and a set of external data sources. The result is a highly parallel multiprocessor system that has multiple parallel high performance input/output ports capable of operating in a distributed fashion. The distributed architecture also permits both processors and external interface ports to access all of the shared data structures associated with the operating system that contain the input/output control information.
摘要翻译：用于多处理器系统的输入/输出系统的分布式架构为多处理器系统的处理器和外部接口端口提供对所有共享硬件资源的平等和民主访问。这允许连接到外部接口端口的一个或多个输入/输出集中器完全访问跨多处理器系统的所有共享硬件资源，而不需要处理器干预。分布式输入/输出系统提供在一组公共共享硬件资源和一组外部数据源之间的数据和控制信息的通信。结果是一个高度并行的多处理器系统，具有多个可以分布式运行的并行高性能输入/输出端口。分布式架构还允许处理器和外部接口端口访问与包含输入/输出控制信息的操作系统相关联的所有共享数据结构。

3. 发明授权

US5625831A Extendible clock mechanism 失效
标题翻译：可扩展时钟机制
公开(公告)号：US5625831A
公开(公告)日：1997-04-29
申请号：US331730
申请日：1994-10-31
申请人： Edward C. Priest , John M. Wastlick
发明人： Edward C. Priest , John M. Wastlick
IPC分类号： G06F9/38 , G06F1/10 , G06F12/06 , G06F13/16 , G06F15/173
CPC分类号： G06F13/1657 , G06F1/10 , G06F13/1663 , G06F15/17337 , G06F15/17381
摘要： A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnection of multiple clusters of processors to a create a floating shared memory effectively combines all three type of memory models, pure shared memory, extended shared memory and distributed shared memory, into a unified parallel processing architecture.
摘要翻译：统一的并行处理架构将多个处理器的可扩展数量的集群连接在一起，以创建高性能并行处理计算机系统。多个处理器被分组到四个或更多个物理上可分离的群集中，每个群集具有由该群集中的所有处理器对称地访问的公共群集共享存储器; 然而，只有一些集群是相互关联的。如果与相对存储器延迟和相对数据局部性相关的某些存储器访问条件可以创建有效的共享存储器并行编程环境，则群集相互互连以形成浮动共享存储器。共享存储器模型可以与可以在单个集群的集群共享存储器中执行的程序一起使用，或者在由包括相邻互连的任何集合的集群共享存储器的扩展共享存储器空间中定义的浮动共享存储器中使用集群。分布式存储器模型可以与要在任何非相邻互连的集群的集群共享存储器中执行的任何程序一起使用。处理器的多个集群的相邻互连以创建浮动共享存储器有效地将所有三种类型的存储器模型，纯共享存储器，扩展共享存储器和分布式共享存储器组合成统一的并行处理架构。

4. 发明授权

US07366854B2 Systems and methods for scheduling memory requests utilizing multi-level arbitration 有权
标题翻译：使用多级仲裁来调度存储器请求的系统和方法
公开(公告)号：US07366854B2
公开(公告)日：2008-04-29
申请号：US10434044
申请日：2003-05-08
申请人： John M. Wastlick , Michael K. Dugan
发明人： John M. Wastlick , Michael K. Dugan
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1626
摘要： In an embodiment, a memory scheduler is provided to process memory requests. The memory scheduler may comprise: a plurality of arbitrators that each select memory requests according to age of the memory requests and whether resources are available for the memory requests; and a second-level arbitrator that selects, for an arbitration round, a series of memory requests made available by the plurality of arbitrators, wherein the second-level arbitrator begins the arbitration round by selecting a memory request from a least recently used (LRU) arbitrator of the plurality of arbitrators.
摘要翻译：在一个实施例中，提供存储器调度器来处理存储器请求。存储器调度器可以包括：多个仲裁器，每个仲裁器根据存储器请求的年龄选择存储器请求以及资源是否可用于存储器请求; 以及第二级仲裁器，用于仲裁回合中由多个仲裁者提供的一系列存储器请求，其中所述第二级仲裁器通过从最近最近使用的（LRU）选择存储器请求开始仲裁循环，多名仲裁员的仲裁员。

5. 发明授权

US07305518B2 Method and system for dynamically adjusting DRAM refresh rate 有权
标题翻译：动态调整DRAM刷新率的方法和系统
公开(公告)号：US07305518B2
公开(公告)日：2007-12-04
申请号：US10969662
申请日：2004-10-20
申请人： Roy Mehdi Zeighami , Brian M. Johnson , John M. Wastlick , David Russel Soper
发明人： Roy Mehdi Zeighami , Brian M. Johnson , John M. Wastlick , David Russel Soper
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G11C11/406 , G11C11/40611 , G11C2211/4061 , Y02D10/14
摘要： One embodiment is a method of dynamically adjusting a rate at which a dynamic random access memory (“DRAM”) module is refreshed in a computer system. The method comprises monitoring a plurality of system conditions; detecting a change in at least one of the monitored system conditions; responsive to the detection, determining an optimum refresh rate for a current state of the computer system; and setting the refresh rate to the determined optimum refresh rate.
摘要翻译：一个实施例是动态地调整在计算机系统中刷新动态随机存取存储器（“DRAM”）模块的速率的方法。该方法包括监视多个系统状况; 检测所监测的系统条件中的至少一个的变化; 响应于所述检测，确定所述计算机系统的当前状态的最佳刷新率; 并将刷新率设置为所确定的最佳刷新率。

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