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    • 4. 发明授权
    • System and method for etching organic anti-reflective coating from a substrate
    • 用于从衬底蚀刻有机抗反射涂层的系统和方法
    • US06296780B1
    • 2001-10-02
    • US08986427
    • 1997-12-08
    • Chun YanYan YeDiana Ma
    • Chun YanYan YeDiana Ma
    • H01L213213
    • H01L21/31116
    • The present invention is embodied in a method and apparatus for etching an organic anti-reflective coating (OARC) layer and a titanium nitride anti-reflective coating (TiN ARC) layer deposited on a substrate located within a processing chamber, without the need for removing the substrate being processed from the processing chamber in which it is situated and without the need for intervening processing steps, such as chamber cleaning operations. The substrate has a base, an underlying oxide layer above the base, an overlying layer above the underlying layer, a middle conductive layer, a TiN ARC layer, and a top OARC layer spun on top of the TiN ARC.
    • 本发明体现在一种用于蚀刻有机抗反射涂层(OARC)层和沉积在位于处理室内的衬底上的氮化钛抗反射涂层(TiN ARC)层的方法和装置中,而不需要去除 基板从其所处理的处理室进行处理,而不需要中间处理步骤,例如室清洁操作。 衬底具有基底,在基底上方的下面的氧化物层,在下层上方的上覆层,中间导电层,TiN ARC层和在TiN ARC顶部旋转的顶部OARC层。
    • 5. 发明申请
    • ALTERNATIVE INTEGRATION SCHEME FOR CMOS S/D SiGe PROCESS
    • CMOS S / D SiGe工艺的替代整合方案
    • US20070287244A1
    • 2007-12-13
    • US11739099
    • 2007-04-24
    • Meihua ShenYonah ChoMark KawaguchiFaran NouriDiana Ma
    • Meihua ShenYonah ChoMark KawaguchiFaran NouriDiana Ma
    • H01L21/8236
    • H01L21/823814H01L21/823864
    • A method for fabricating a semiconductor device with adjacent PMOS and NMOS devices on a substrate includes forming a PMOS gate electrode with a PMOS hardmask on a semiconductor substrate with a PMOS gate dielectric layer in between, forming an NMOS gate electrode with an NMOS hardmask on a semiconductor substrate with an NMOS gate dielectric layer in between, forming an oxide liner over a portion of the PMOS gate electrode and over a portion of the NMOS gate electrode, forming a lightly doped N-Halo implant, depositing a nitride layer over the oxide liner, depositing photoresist on the semiconductor substrate in a pattern that covers the NMOS device, etching the nitride layer from the PMOS device, wherein the etching nitride layer leaves a portion of the nitride layer on the oxide liner, etching semiconductor substrate to form a Si recess, and depositing SiGe into the Si recesses, wherein the SiGe and the nitride layer enclose the oxide liner. The method can also include implanting in the semiconductor substrate a source and drain region for the PMOS.
    • 一种用于在衬底上制造具有相邻PMOS和NMOS器件的半导体器件的方法包括在半导体衬底上形成具有PMOS硬掩模的PMOS栅电极,其间具有PMOS栅极介电层,在NMOS栅极上形成NMOS栅极 半导体衬底,其间具有NMOS栅极介电层,在PMOS栅电极的一部分上方和NMOS栅电极的一部分之上形成氧化物衬垫,形成轻掺杂的N-Halo注入,在氧化物衬垫上沉积氮化物层 以覆盖所述NMOS器件的图案沉积在所述半导体衬底上的光致抗蚀剂,从所述PMOS器件蚀刻所述氮化物层,其中所述蚀刻氮化物层离开所述氧化物衬底上的所述氮化物层的一部分,蚀刻半导体衬底以形成Si凹槽 并且将SiGe沉积到Si凹部中,其中SiGe和氮化物层包围氧化物衬垫。 该方法还可以包括在半导体衬底中注入用于PMOS的源极和漏极区域。
    • 7. 发明授权
    • Method for recovering metal from etch by-products
    • 从蚀刻副产物中回收金属的方法
    • US06413389B1
    • 2002-07-02
    • US09467295
    • 1999-12-17
    • Hong ShihDanny LuNianci HanLi XuDiana Ma
    • Hong ShihDanny LuNianci HanLi XuDiana Ma
    • C02F1461
    • C22B11/042Y02P10/214
    • A method and assembly for recovering a metal from by-products produced from etching a metal (e.g., platinum, iridium, aluminum, etc.) in a plasma processing chamber. The method includes recovering from the plasma processing chamber a deposit of the by-products containing the metal. The deposit is dissolved in an acid, and the metal is recovered from the acid by inserting a working electrode, a reference electrode, and a counter electrode into the acid and applying a difference in potential between the working and reference electrodes to cause current to flow through the working and counter electrodes and the metal to be removed from the liquid and deposit on the working electrode. The metal is removed from the working electrode to recover the metal. The assembly for recovering the metal from the by-products includes a potentiostat for effecting a difference in potential between the working and reference electrodes and causing current to flow through the working and counter electrodes in response to the difference in potential between the working and reference electrodes.
    • 一种用于从在等离子体处理室中蚀刻金属(例如,铂,铱,铝等)产生的副产物中回收金属的方法和组件。 该方法包括从等离子体处理室回收含有金属的副产物的沉积物。 将沉积物溶解在酸中,通过将工作电极,参比电极和对电极插入酸中并在工作电极和参考电极之间施加电位差以使电流流动从酸中回收金属 通过工作电极和对电极以及从液体中除去的金属沉积在工作电极上。 从工作电极上除去金属以回收金属。 用于从副产物中回收金属的组件包括用于实现工作电极和参考电极之间的电位差的恒电位仪,并且响应于工作电极和参考电极之间的电位差而导致电流流过工作电极和对电极 。
    • 8. 发明授权
    • RF plasma etch reactor with internal inductive coil antenna and
electrically conductive chamber walls
    • RF等离子体蚀刻反应器,具有内部感应线圈天线和导电室壁
    • US6071372A
    • 2000-06-06
    • US869798
    • 1997-06-05
    • Yan YeDonald OlgadoAvi TepmanDiana MaGerald YinPeter LoewenhardtJeng H. HwangSteve Mak
    • Yan YeDonald OlgadoAvi TepmanDiana MaGerald YinPeter LoewenhardtJeng H. HwangSteve Mak
    • H05H1/46H01J37/32H01L21/302C23F1/02C23C16/00
    • H01J37/32477H01J37/321
    • An RF plasma etch reactor having an etch chamber with electrically conductive walls and a protective layer forming the portion of the walls facing the interior of the chamber. The protective layer prevents sputtering of material from the chamber walls by a plasma formed within the chamber. The etch reactor also has an inductive coil antenna disposed within the etch chamber which is used to generate the plasma by inductive coupling. Like the chamber walls, the inductive coil antenna is constructed to prevent sputtering of the material making up the antenna by the plasma. The coil antenna can take on any configuration (e.g. location, shape, orientation) that is necessary to achieve a desired power deposition pattern within the chamber. Examples of potential coil antenna configurations for achieving the desired power deposition pattern include constructing the coil antenna with a unitary or a segmented structure. The segmented structure involves the use of at least two coil segments wherein each segment is electrically isolated from the other segments and connected to a separate RF power signal. The unitary coil antenna or each of the coil segments can have a planar shape, a cylindrical shape, a truncated conical shape, a dome shape, or any combination thereof. The conductive walls are electrically grounded to serve as an electrical ground (i.e. anode) for a workpiece-supporting pedestal which is connected to a source of RF power to create a bias voltage at the surface of the workpiece.
    • RF等离子体蚀刻反应器具有具有导电壁的蚀刻室和形成面向腔室内部的部分壁的保护层。 保护层防止在室内形成的等离子体从室壁溅射材料。 蚀刻反应器还具有设置在蚀刻室内的感应线圈天线,其用于通过感应耦合产生等离子体。 类似于室壁,感应线圈天线被构造成防止由等离子体溅射构成天线的材料。 线圈天线​​可以承受在室内实现期望的功率沉积图案所必需的任何配置(例如位置,形状,取向)。 用于实现期望的功率沉积模式的电位线圈天线配置的示例包括以整体或分段结构构造线圈天线。 分段结构涉及使用至少两个线圈段,其中每个段与其它段电隔离并连接到单独的RF功率信号。 单线圈天线或每个线圈段可以具有平面形状,圆柱形,截顶圆锥形,圆顶形或其任何组合。 导电壁电接地以用作工件支撑基座的电接地(即阳极),工件支撑基座连接到RF功率源,以在工件的表面产生偏置电压。
    • 10. 发明授权
    • Method for monitoring the quality of a protective coating in a reactor chamber
    • 监测反应室中保护涂层质量的方法
    • US06466881B1
    • 2002-10-15
    • US09298073
    • 1999-04-22
    • Hong ShihJoe SommersDiana Ma
    • Hong ShihJoe SommersDiana Ma
    • C23C1434
    • H01J37/32477C23C14/564C23C16/4404
    • A method for determining the quality of a protective coating or layer on a structure inside of a reactor chamber. The method includes generating a basis, such as a standard scatter band of impedance, as an acceptable standard for the quality of a protective layer on the inside of a reactor chamber. At least one substrate is processed within a reactor chamber containing a protective coating for protecting the inside of the reactor chamber during processing of the substrate. The method further includes determining the quality of the protective coating, such as by measuring protective characteristics of the protective coating. A method for on-line monitoring of a quality of a coating on the inside of a reactor chamber.
    • 一种用于确定反应器室内的结构上的保护涂层或层的质量的方法。 该方法包括产生诸如标准散射带阻抗的基准,作为反应室内部的保护层质量的可接受的标准。 在包含保护涂层的反应器室内处理至少一个基板,以在基板的加工期间保护反应室的内部。 该方法还包括确定保护涂层的质量,例如通过测量保护涂层的保护特性。 用于在线监测反应室内部的涂层质量的方法。