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1. 发明授权

US07669155B2 Generic methodology to support chip level integration of IP core instance constraints in integrated circuits 有权
标题翻译：支持集成电路中IP核实例约束的芯片级集成的通用方法
公开(公告)号：US07669155B2
公开(公告)日：2010-02-23
申请号：US11728366
申请日：2007-03-26
申请人： Balaji Ganesan , David Vinke , Ekambaram Balaji , Nicholas A. Oleksinski
发明人： Balaji Ganesan , David Vinke , Ekambaram Balaji , Nicholas A. Oleksinski
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.
摘要翻译：提供了一种用于生成和使用可以在集成电路设计中实例化的用于IP核的时序约束模板的方法和装置。模板包括用于相应IP核的输入和输出的多个时序约束语句。所述语句中的至少一个包括可配置变量，其中所述时序约束模板可通过所述集成电路设计中的所述IP核的多个实例中的每一个的所述变量来配置。

2. 发明申请

US20090125769A1 ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT 有权
标题翻译：用于转换延迟故障测试模式的片上电路与启动关闭移位
公开(公告)号：US20090125769A1
公开(公告)日：2009-05-14
申请号：US11939573
申请日：2007-11-14
申请人： Thai-Minh Nguyen , William Shen , David Vinke , Christopher Coleman
发明人： Thai-Minh Nguyen , William Shen , David Vinke , Christopher Coleman
IPC分类号： G06F11/25
CPC分类号： G01R31/318594 , G01R31/318552 , G11C29/10 , G11C29/56 , G11C29/56004 , G11C29/56012 , G11C2029/3602
摘要： A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.
摘要翻译：时钟脉冲控制器包括用于接收测试时钟脉冲的测试时钟脉冲输入。扫描使能输入接收具有第一状态和第二状态的扫描使能信号。触发脉冲输入接收触发脉冲。时钟脉冲输出在接收到紧跟在触发脉冲之后的预定数量的测试时钟脉冲之后立即从测试时钟脉冲产生启动时钟脉冲和捕获时钟脉冲。延迟扫描使能输出产生延迟的扫描使能信号，其在启动时钟脉冲的前沿和捕获时钟脉冲的前沿之间从第一状态转换到第二状态。

3. 发明授权

US07152194B2 Method and circuit for scan testing latch based random access memory 有权
标题翻译：用于扫描测试基于锁存器的随机存取存储器的方法和电路
公开(公告)号：US07152194B2
公开(公告)日：2006-12-19
申请号：US10645900
申请日：2003-08-20
申请人： David Vinke , Ekambaram Balaji , Giuseppe Fornaciari
发明人： David Vinke , Ekambaram Balaji , Giuseppe Fornaciari
IPC分类号： G01R31/317 , G01R31/316
CPC分类号： G11C29/48 , G11C2029/3202
摘要： A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.
摘要翻译：基于锁存器的随机存取存储器包括输入数据寄存器; 耦合到输入数据寄存器的输入数据缓冲器; 耦合到所述输入数据缓冲器的锁存器阵列; 以及锁存阵列旁路多路复用器，用于响应于存储器扫描模式信号选择输入数据缓冲器和锁存器阵列之一，以在逻辑扫描测试期间从输入数据缓冲器生成基于锁存器的随机存取存储器的第一数据输出，以及在存储器扫描测试期间，来自锁存器阵列的基于锁存器的随机存取存储器的第二数据输出。

4. 发明申请

US20100097875A1 Enhanced Power Distribution in an Integrated Circuit 失效
标题翻译：集成电路中增强的功率分配
公开(公告)号：US20100097875A1
公开(公告)日：2010-04-22
申请号：US12254421
申请日：2008-10-20
申请人： David Vinke , Michael N. Dillon , Bret Alan Oeltjen , Uday Anumalachetty , Thomas Mathews Antisseril
发明人： David Vinke , Michael N. Dillon , Bret Alan Oeltjen , Uday Anumalachetty , Thomas Mathews Antisseril
IPC分类号： G11C5/14 , H01L21/60
CPC分类号： G11C5/063 , G11C8/10 , H01L2924/0002 , H01L2924/14 , H01L2924/1433 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit. The power mesh power connection structure is operative to connect the first and second power rails of the first plurality of standard cells to the voltage supply and voltage return, respectively, and is configured so as to reduce a first voltage differential between respective first power rails of the standard cells and to reduce a second voltage differential between respective second power rails of the standard cells.
摘要翻译：用于向集成电路中的一个或多个标准单元分配功率的集成电路结构包括耦合到该单元的第一多个标准单元和功率网格功率连接结构。每个标准单元包括分别连接到标准单元的电压源和电压返回的第一和第二电源轨。标准细胞子集中的每个标准细胞被布置成与至少两个其它标准细胞直接邻接，并且至少第一和第二末端细胞被布置成与第一多个标准细胞的至少一个其它标准细胞直接邻接。功率网格功率连接结构包括形成在集成电路中的多个不同导电层中的多个导电元件。功率网格电力连接结构可操作以将第一多个标准单元的第一和第二电力轨分别连接到电压供应和电压返回，并且被配置为减小相应的第一电力轨之间的第一电压差并且减小标准单元的相应的第二电源轨之间的第二电压差。

5. 发明授权

US07233540B1 Latch-based random access memory (LBRAM) with tri-state banking and contention avoidance 有权
标题翻译：基于锁存的随机存取存储器（LBRAM），具有三态银行和争用避免
公开(公告)号：US07233540B1
公开(公告)日：2007-06-19
申请号：US11237059
申请日：2005-09-27
申请人： David Vinke , Bret A. Oeltjen , Michael N. Dillon
发明人： David Vinke , Bret A. Oeltjen , Michael N. Dillon
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C11/419
摘要： A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously. Avoiding concurrent activity of the enable signals eliminates contention on the tri-state output bit lines, and thereby prevents the mutually coupled tri-state bit lines output from the first and second tri-state buffers from being active at the same time. Placing a delay between activity minimizes contention on the mutually coupled, buffered bit line.
摘要翻译：诸如随机存取存储器（RAM）的所公开的存储器具有包括第一存储体和第二存储体的多个存储体，每个存储体具有被配置为存储数据的多个锁存单元。第一个银行有一个第一个位线，第二个银行有一个第二个位线。第一三态缓冲器具有耦合到第一位线的输入节点，耦合以接收第一使能信号的使能节点和耦合到三态位线的输出节点。第二三状态缓冲器具有耦合到第二位线的输入节点，耦合以接收第二使能信号的使能节点和耦合到三态位线的输出节点。启用信号生成逻辑使用地址信号的一部分来产生第一和第二使能信号，使得第一和第二使能信号不同时处于活动状态。避免使能信号的并行活动消除了对三态输出位线的争用，从而防止从第一和第二三态缓冲器输出的相互耦合的三态位线同时被激活。在活动之间延迟最小化相互耦合的缓冲位线上的争用。

6. 发明申请

US20050268185A1 Method and apparatus for high speed testing of latch based random access memory 失效
标题翻译：用于基于锁存器的随机存取存储器的高速测试的方法和装置
公开(公告)号：US20050268185A1
公开(公告)日：2005-12-01
申请号：US10901609
申请日：2004-07-28
申请人： David Vinke , Ekambaram Balaji
发明人： David Vinke , Ekambaram Balaji
IPC分类号： G11C29/00 , G11C29/32
CPC分类号： G11C29/1201 , G11C11/41 , G11C29/32 , G11C2029/3202
摘要： A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.
摘要翻译：用于测试基于锁存器的随机存取存储器的方法和装置包括以下步骤：产生用于测试基于锁存器的随机存取存储器的扫描使能信号，并产生用于测试基于锁存器的随机存取存储器的扫描时钟信号，其中扫描时钟信号具有第一扫描时移位周期的周期和捕获周期的第二扫描时钟周期。

7. 发明申请

US20050041460A1 Method and circuit for scan testing latch based random access memory 有权
标题翻译：用于扫描测试基于锁存器的随机存取存储器的方法和电路
公开(公告)号：US20050041460A1
公开(公告)日：2005-02-24
申请号：US10645900
申请日：2003-08-20
申请人： David Vinke , Ekambaram Balaji , Giuseppe Fornaciari
发明人： David Vinke , Ekambaram Balaji , Giuseppe Fornaciari
IPC分类号： G11C29/48 , G11C11/00
CPC分类号： G11C29/48 , G11C2029/3202
摘要： A latch based random access memory includes an input data register; an input data buffer coupled to the input data register; a latch array coupled to the input data buffer; and a latch array bypass multiplexer for selecting one of the input data buffer and the latch array in response to a memory scan mode signal to generate a first data output of the latch based random access memory from the input data buffer during logic scan testing and a second data output of the latch based random access memory from the latch array during memory scan testing.
摘要翻译：基于锁存器的随机存取存储器包括输入数据寄存器; 耦合到输入数据寄存器的输入数据缓冲器; 耦合到所述输入数据缓冲器的锁存器阵列; 以及锁存阵列旁路多路复用器，用于响应于存储器扫描模式信号选择输入数据缓冲器和锁存器阵列之一，以在逻辑扫描测试期间从输入数据缓冲器生成基于锁存器的随机存取存储器的第一数据输出，以及在存储器扫描测试期间，来自锁存器阵列的基于锁存器的随机存取存储器的第二数据输出。

8. 发明申请

US20080244491A1 Generic methodology to support chip level integration of IP core instance constraints in integrated circuits 有权
标题翻译：支持集成电路中IP核实例约束的芯片级集成的通用方法
公开(公告)号：US20080244491A1
公开(公告)日：2008-10-02
申请号：US11728366
申请日：2007-03-26
申请人： Balaji Ganesan , David Vinke , Ekambaram Balaji , Nicholas A. Oleksinski
发明人： Balaji Ganesan , David Vinke , Ekambaram Balaji , Nicholas A. Oleksinski
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.
摘要翻译：提供了一种用于生成和使用可以在集成电路设计中实例化的用于IP核的时序约束模板的方法和装置。模板包括用于相应IP核的输入和输出的多个时序约束语句。所述语句中的至少一个包括可配置变量，其中所述时序约束模板可通过所述集成电路设计中的所述IP核的多个实例中的每一个的所述变量来配置。

9. 发明授权

US07266021B1 Latch-based random access memory (LBRAM) tri-state banking architecture 有权
标题翻译：基于锁存的随机存取存储器（LBRAM）三态银行架构
公开(公告)号：US07266021B1
公开(公告)日：2007-09-04
申请号：US11237064
申请日：2005-09-27
申请人： David Vinke , Bret A. Oeltjen , Ekambaram Balaji
发明人： David Vinke , Bret A. Oeltjen , Ekambaram Balaji
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/12 , G11C8/12
摘要： A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state output bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state output bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals. The memory produces an output signal dependent upon the enable signal generation logic output, and thus upon a logic level of the tri-state output bit line.
摘要翻译：诸如随机存取存储器（RAM）的所公开的存储器具有包括第一存储体和第二存储体的多个存储体，每个存储体具有被配置为存储数据的多个锁存单元。第一个银行有一个第一个位线，第二个银行有一个第二个位线。第一三态缓冲器具有耦合到第一位线的输入节点，耦合以接收第一使能信号的使能节点和耦合到三态输出位线的输出节点。第二三状态缓冲器具有耦合到第二位线的输入节点，耦合以接收第二使能信号的使能节点和耦合到三态输出位线的输出节点。使能信号生成逻辑使用地址信号的一部分来产生第一和第二使能信号。存储器根据使能信号产生逻辑输出产生输出信号，从而产生三态输出位线的逻辑电平。

10. 发明授权

US07231563B2 Method and apparatus for high speed testing of latch based random access memory 失效
标题翻译：用于基于锁存器的随机存取存储器的高速测试的方法和装置
公开(公告)号：US07231563B2
公开(公告)日：2007-06-12
申请号：US10901609
申请日：2004-07-28
申请人： David Vinke , Ekambaram Balaji
发明人： David Vinke , Ekambaram Balaji
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/1201 , G11C11/41 , G11C29/32 , G11C2029/3202
摘要： A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.
摘要翻译：用于测试基于锁存器的随机存取存储器的方法和装置包括以下步骤：产生用于测试基于锁存器的随机存取存储器的扫描使能信号，并产生用于测试基于锁存器的随机存取存储器的扫描时钟信号，其中扫描时钟信号具有第一扫描时移位周期的周期和捕获周期的第二扫描时钟周期。

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