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1. 发明授权

US08429586B2 Basic cell architecture for structured ASICs 失效
标题翻译：结构化ASIC的基本单元架构
公开(公告)号：US08429586B2
公开(公告)日：2013-04-23
申请号：US13424747
申请日：2012-03-20
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl A. Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary S. Delp , Scott A. Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl A. Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary S. Delp , Scott A. Peterson
IPC分类号： G06F17/50
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个单元或多个单元内的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。

2. 发明申请

US20120175683A1 Basic Cell Architecture For Structured ASICs 失效
标题翻译：结构化ASIC的基本单元架构
公开(公告)号：US20120175683A1
公开(公告)日：2012-07-12
申请号：US13424747
申请日：2012-03-20
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
IPC分类号： H01L27/105
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了具有多个可固定晶体管的单元的基本单元电路架构，其可配置用于形成逻辑器件以及结构化ASIC内的单端口和双端口存储器件。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个单元或多个单元内的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或二者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，更能适应现代的SoC。

3. 发明申请

US20100097875A1 Enhanced Power Distribution in an Integrated Circuit 失效
标题翻译：集成电路中增强的功率分配
公开(公告)号：US20100097875A1
公开(公告)日：2010-04-22
申请号：US12254421
申请日：2008-10-20
申请人： David Vinke , Michael N. Dillon , Bret Alan Oeltjen , Uday Anumalachetty , Thomas Mathews Antisseril
发明人： David Vinke , Michael N. Dillon , Bret Alan Oeltjen , Uday Anumalachetty , Thomas Mathews Antisseril
IPC分类号： G11C5/14 , H01L21/60
CPC分类号： G11C5/063 , G11C8/10 , H01L2924/0002 , H01L2924/14 , H01L2924/1433 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit. The power mesh power connection structure is operative to connect the first and second power rails of the first plurality of standard cells to the voltage supply and voltage return, respectively, and is configured so as to reduce a first voltage differential between respective first power rails of the standard cells and to reduce a second voltage differential between respective second power rails of the standard cells.
摘要翻译：用于向集成电路中的一个或多个标准单元分配功率的集成电路结构包括耦合到该单元的第一多个标准单元和功率网格功率连接结构。每个标准单元包括分别连接到标准单元的电压源和电压返回的第一和第二电源轨。标准细胞子集中的每个标准细胞被布置成与至少两个其它标准细胞直接邻接，并且至少第一和第二末端细胞被布置成与第一多个标准细胞的至少一个其它标准细胞直接邻接。功率网格功率连接结构包括形成在集成电路中的多个不同导电层中的多个导电元件。功率网格电力连接结构可操作以将第一多个标准单元的第一和第二电力轨分别连接到电压供应和电压返回，并且被配置为减小相应的第一电力轨之间的第一电压差并且减小标准单元的相应的第二电源轨之间的第二电压差。

4. 发明授权

US07233540B1 Latch-based random access memory (LBRAM) with tri-state banking and contention avoidance 有权
标题翻译：基于锁存的随机存取存储器（LBRAM），具有三态银行和争用避免
公开(公告)号：US07233540B1
公开(公告)日：2007-06-19
申请号：US11237059
申请日：2005-09-27
申请人： David Vinke , Bret A. Oeltjen , Michael N. Dillon
发明人： David Vinke , Bret A. Oeltjen , Michael N. Dillon
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C11/419
摘要： A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously. Avoiding concurrent activity of the enable signals eliminates contention on the tri-state output bit lines, and thereby prevents the mutually coupled tri-state bit lines output from the first and second tri-state buffers from being active at the same time. Placing a delay between activity minimizes contention on the mutually coupled, buffered bit line.
摘要翻译：诸如随机存取存储器（RAM）的所公开的存储器具有包括第一存储体和第二存储体的多个存储体，每个存储体具有被配置为存储数据的多个锁存单元。第一个银行有一个第一个位线，第二个银行有一个第二个位线。第一三态缓冲器具有耦合到第一位线的输入节点，耦合以接收第一使能信号的使能节点和耦合到三态位线的输出节点。第二三状态缓冲器具有耦合到第二位线的输入节点，耦合以接收第二使能信号的使能节点和耦合到三态位线的输出节点。启用信号生成逻辑使用地址信号的一部分来产生第一和第二使能信号，使得第一和第二使能信号不同时处于活动状态。避免使能信号的并行活动消除了对三态输出位线的争用，从而防止从第一和第二三态缓冲器输出的相互耦合的三态位线同时被激活。在活动之间延迟最小化相互耦合的缓冲位线上的争用。

5. 发明授权

US6093214A Standard cell integrated circuit layout definition having functionally uncommitted base cells 失效
标题翻译：标准单元集成电路布局定义具有功能上未提交的基本单元
公开(公告)号：US6093214A
公开(公告)日：2000-07-25
申请号：US31956
申请日：1998-02-26
申请人： Michael N. Dillon
发明人： Michael N. Dillon
IPC分类号： G06F17/50 , H01L27/118
CPC分类号： H01L27/11807 , G06F17/5068
摘要： A method of forming a layout definition of a semiconductor integrated circuit includes generating a netlist of functionally committed standard cell instances and the electrical interconnections between the standard cell instances. The standard cell instances are then placed in a layout pattern. Also, functionally uncommitted base cells are place with the standard cell instances in the layout pattern. The base cell instances may be metalized, if needed, in later processing steps to implement design changes by adding additional logical functions.
摘要翻译：形成半导体集成电路的布局定义的方法包括生成功能承诺标准单元实例的网表和标准单元实例之间的电互连。然后将标准单元格实例放置在布局模式中。而且，功能上未提交的基本单元格与布局模式中的标准单元格实例一起放置。如果需要，基本单元实例可以在稍后的处理步骤中进行金属化，以通过添加附加的逻辑功能来实现设计更改。

6. 发明授权

US08166440B1 Basic cell architecture for structured application-specific integrated circuits 失效
标题翻译：用于结构化应用专用集成电路的基本单元架构
公开(公告)号：US08166440B1
公开(公告)日：2012-04-24
申请号：US12139974
申请日：2008-06-16
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
IPC分类号： G06F17/50
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了一种基本单元电路架构，其具有可配置用于形成结构化ASIC内的逻辑器件和/或单/双端口存储器件的固定晶体管的多个单元。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个电池内和/或跨多个电池的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或两者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，并且更完全适用于现代SoC。

7. 发明授权

US07269803B2 System and method for mapping logical components to physical locations in an integrated circuit design environment 有权
标题翻译：将逻辑组件映射到集成电路设计环境中的物理位置的系统和方法
公开(公告)号：US07269803B2
公开(公告)日：2007-09-11
申请号：US10740284
申请日：2003-12-18
申请人： Khosro Khakzadi , Chris J. Tremel , Michael N. Dillon
发明人： Khosro Khakzadi , Chris J. Tremel , Michael N. Dillon
IPC分类号： G06F17/50 , H01L23/544
CPC分类号： G06F17/5072
摘要： A system and method for mapping Intellectual Property (IP) components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a legal location for the IP component that is near to the target location. The IP component is mapped to the legal location.
摘要翻译：将知识产权（IP）组件映射到预制芯片片上的系统和方法允许用户选择用于将IP组件放置在片上的目标位置。搜索预制芯片切片的切片定义，以获得靠近目标位置的IP组件的合法位置。 IP组件映射到合法位置。

8. 发明授权

US06934171B2 Semiconductor integrated circuit having voltage-down circuit regulator and charge sharing 失效
公开(公告)号：US06934171B2
公开(公告)日：2005-08-23
申请号：US10672125
申请日：2003-09-26
申请人： Michael N. Dillon , Bret A. Oeltjen
发明人： Michael N. Dillon , Bret A. Oeltjen
IPC分类号： G05F1/40 , H02M1/00
CPC分类号： G05F1/40
摘要： An integrated circuit is provided, which includes first, second and third power supply conductors. The second power supply conductor has a higher voltage than the first power supply conductor, and the third power supply conductor has a higher voltage than the second power supply conductor. A high voltage power supply decoupling capacitor is coupled between the first and third power supply conductors. A low voltage power supply decoupling capacitor coupled between the first and second power supply conductors. A voltage reducer is coupled between the second and third power supply conductors. A plurality of semiconductor devices is biased between the first and second power supply conductors.

9. 发明授权

US07404154B1 Basic cell architecture for structured application-specific integrated circuits 有权
标题翻译：用于结构化应用专用集成电路的基本单元架构
公开(公告)号：US07404154B1
公开(公告)日：2008-07-22
申请号：US11189026
申请日：2005-07-25
申请人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
发明人： Ramnath Venkatraman , Michael N. Dillon , David A. Gardner , Carl Anthony Monzel, III , Subramanian Ramesh , Robert C. Armstrong , Gary Scott Delp , Scott Allen Peterson
IPC分类号： G06F17/50
CPC分类号： H03K19/1735 , G06F2217/64 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.
摘要翻译：提供了一种基本单元电路架构，其具有可配置用于形成结构化ASIC内的逻辑器件和/或单/双端口存储器件的固定晶体管的多个单元。通过在固定结构上方形成可变互连层来实现随后的集成电路的不同配置。电路架构可以实现单个电池内和/或跨多个电池的晶体管的互连。互连可以配置成形成基本逻辑门，以及更复杂的数字和模拟子系统。此外，每个单元包含可以可变地耦合以实现诸如SRAM器件的存储器件的晶体管的布局。通过具有形成逻辑电路元件，存储器件或两者的能力，电路架构既是以内存为中心的，也是以逻辑为中心的，并且更完全适用于现代SoC。

10. 发明授权

US07231625B2 Method and apparatus for use of hidden decoupling capacitors in an integrated circuit design 有权
标题翻译：在集成电路设计中使用隐藏去耦电容器的方法和装置
公开(公告)号：US07231625B2
公开(公告)日：2007-06-12
申请号：US10952194
申请日：2004-09-28
申请人： Michael N. Dillon , Christopher J. Tremel
发明人： Michael N. Dillon , Christopher J. Tremel
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor cell has a width, which is greater than that of a single base cell location and which is abstracted from the base layer layout pattern. A cell library defines a plurality of cells, including a macro cell having open rows consistent with the rows in the base layer layout pattern that are reserved for the decoupling capacitor cells. The width of each decoupling capacitor cell is abstracted from the macro cell. Cells from the cell library, including the macro cell, are placed within a design layout pattern relative to the base layer layout pattern. An area consumed by the macro cell within the design layout pattern is independent of the width of the decoupling capacitor cells.
摘要翻译：提供了一种用于将电池放置在集成电路布局图案中的方法和装置。基层布局图形定义基本单元位置和基层元素的阵列，其中阵列中的一些行的至少部分被保留用于去耦合电容器单元。每个去耦电容器单元的宽度大于单个基本单元位置的宽度，并且从基层布局图案中抽取出来。单元库定义多个单元，包括具有与为去耦电容器单元保留的基层布局图案中的行一致的开放行的宏单元。每个去耦电容器单元的宽度从宏单元中抽象出来。来自细胞库的细胞（包括宏细胞）相对于基底层布局图案被放置在设计布局图案内。设计布局图案内宏单元消耗的面积与去耦电容单元的宽度无关。

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