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1. 发明授权

US07831816B2 Non-destructive sideband reading of processor state information 有权
标题翻译：非破坏性边带读取处理器状态信息
公开(公告)号：US07831816B2
公开(公告)日：2010-11-09
申请号：US12130990
申请日：2008-05-30
申请人： Wallace P. Montgomery , David F. Tobias , Michael T. Clark
发明人： Wallace P. Montgomery , David F. Tobias , Michael T. Clark
IPC分类号： G06F9/312
CPC分类号： G06F11/3656 , G06F9/30003
摘要： A processor receives a command via a sideband interface on the processor to read processor state information, e.g., CPUID information. The sideband interface provides the command information to a microcode engine in the processor that executes the command to retrieve the designated processor state information at an appropriate instruction boundary and retrieves the processor state information. That processor information is stored in local buffers in the sideband interface to avoid modifying processor state. After the microcode engine completes retrieval of the information and the sideband interface command is complete, execution returns to the normal flow in the processor. Thus, the processor state information may be obtained non-destructively during processor runtime.
摘要翻译：处理器经由处理器上的边带接口接收命令以读取处理器状态信息，例如CPUID信息。边带接口向处理器中的微代码引擎提供命令信息，执行命令以在适当的指令边界检索指定的处理器状态信息并检索处理器状态信息。该处理器信息存储在边带接口中的本地缓冲区中，以避免修改处理器状态。在微代码引擎完成信息的检索并且边带接口命令完成之后，执行返回处理器中的正常流程。因此，可以在处理器运行时期间非破坏性地获得处理器状态信息。

2. 发明授权

US07188261B1 Processor operational range indicator 有权
标题翻译：处理器运行范围指示器
公开(公告)号：US07188261B1
公开(公告)日：2007-03-06
申请号：US10132614
申请日：2002-04-25
申请人： David F. Tobias , Morrie Altmejd
发明人： David F. Tobias , Morrie Altmejd
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： An integrated circuit device provides an operational set point indicator. The operational set point indicator is utilized for obtaining a plurality of operational set points. Each of the plurality of operational set points can be a pair of an operational voltage and an operational frequency for application to the integrated circuit device. The operational set point indicator can be, for example, a Schmoo Class Register, a Device Identification Register, or actual operating condition information of the integrated circuit device. The Schmoo Class Register and the Device Identification Register are utilized to identify a performance state table in memory. The actual operating conditional information can be one or more entire Schmoo Plots for the device or a subset of such information. Operational set points are used during operation of the integrated circuit device, for example, in power management applications.
摘要翻译：集成电路装置提供操作设定点指示器。操作设定点指示符用于获得多个操作设定点。多个操作设定点中的每一个可以是用于应用于集成电路装置的一对工作电压和工作频率。操作设定点指示符可以是例如Schmoo类寄存器，设备识别寄存器或集成电路设备的实际操作条件信息。 Schmoo类寄存器和器件识别寄存器用于识别存储器中的性能状态表。实际的操作条件信息可以是设备的一个或多个整个Schmoo图或这样的信息的子集。在集成电路设备的操作期间使用操作设定点，例如在电源管理应用中。

3. 发明授权

US06188241B1 Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface 有权
标题翻译：微控制器具有逻辑块，其可配置为执行选定的逻辑功能并根据预定义的硬件接口产生耦合到对应的I / O焊盘的输出信号
公开(公告)号：US06188241B1
公开(公告)日：2001-02-13
申请号：US09311448
申请日：1999-05-14
申请人： Lloyd W. Gauthier , Carl K. Wakeland , Faheem Hayat , David F. Tobias
发明人： Lloyd W. Gauthier , Carl K. Wakeland , Faheem Hayat , David F. Tobias
IPC分类号： H03K19177
CPC分类号： G06F15/7867
摘要： A microcontroller is presented having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface. The microcontroller includes a central processing unit (CPU), a first set of I/O pads, and a configurable logic block (CLB) all formed upon a single monolithic semiconductor substrate. The CPU is configured to execute instructions, preferably x86 instructions. The CPU produces CPU output signals during instruction execution. The CLB is coupled between the CPU output signals and the first set of I/O pads, and is configurable to perform a logic function selected from a predefined set of logic functions. Each member of the set of logic functions has an associated hardware interface including a signal table which defines a correspondence between CLB input/output signals and members of the first set of I/O pads. The microcontroller also preferably includes a test/program core coupled to a second set of I/O pads and to the CLB. The test/program core produces programming signals in response to signals received via the second set of I/O pads. The programming signals cause the CLB to perform the selected logic function. When programmed, the CLB produces CLB output signals in response to the CPU output signals. Each of the CLB output signals is coupled to one or more of the members of the first set of I/O pads according to the hardware interface of the selected logic function.
摘要翻译：呈现具有可配置为执行选定逻辑功能并根据预定义的硬件接口产生耦合到相应I / O焊盘的输出信号的逻辑块的微控制器。微控制器包括中央处理单元（CPU），第一组I / O焊盘以及全部形成在单个单片半导体衬底上的可配置逻辑块（CLB）。 CPU配置为执行指令，最好是x86指令。 CPU在指令执行过程中产生CPU输出信号。 CLB耦合在CPU输出信号和第一组I / O焊盘之间，并且可配置为执行从预定义的一组逻辑功能中选择的逻辑功能。逻辑功能集合中的每个成员具有相关联的硬件接口，其包括定义CLB输入/输出信号与第一组I / O焊盘组件之间的对应关系的信号表。微控制器还优选地包括耦合到第二组I / O焊盘和CLB的测试/程序核心。测试/程序核心响应于经由第二组I / O焊盘接收到的信号产生编程信号。编程信号使CLB执行选定的逻辑功能。当编程时，CLB响应于CPU输出信号产生CLB输出信号。根据所选择的逻辑功能的硬件接口，每个CLB输出信号被耦合到第一组I / O焊盘的一个或多个成员。

4. 发明授权

US5978903A Apparatus and method for automatically accessing a dynamic RAM for system management interrupt handling 失效
标题翻译：用于自动访问动态RAM的装置和方法，用于系统管理中断处理
公开(公告)号：US5978903A
公开(公告)日：1999-11-02
申请号：US914511
申请日：1997-08-19
申请人： Michael Scott Quimby , David F. Tobias
发明人： Michael Scott Quimby , David F. Tobias
IPC分类号： G06F12/06 , G06F12/08
CPC分类号： G06F12/0623
摘要： A System Management Mode is transparent to normal system operations and dynamic RAM (DRAM) is available in the Upper Memory Block address range that is normally not accessible in many configurations. Therefore, the DRAM is advantageously used to attain System Management Mode read/write storage requirements. The System Management Mode time-multiplexes the Upper Memory Block memory-mapped address space with other non-DRAM resources in a timely manner by switching the SMM memory into the DRAM Upper Memory Block space in a "just in time" (JIT) basis. The JIT operation is achieved by latching the first memory address emitted from the CPU after SMM entry. The first memory address is designated as the top address of a memory block that extends downward into memory address space, defining an SMM memory range. All subsequent memory accesses that are addressed within the SMM memory range are directed to DRAM Upper Memory Block regardless of any other memory-mapped resources that normally reside within the same range of addresses as the SMM memory range. Upon the occurrence of an SMM resume instruction, the memory device mapping is automatically restored to the configuration existing prior to SMM activation. Using this technique, memory-mapped address space that is normally used for non-SMM purposes is employed for SMM operations in a method that is transparent to the system and application programs. Advantageously, DRAM that may not be normally available for usage due to the presence of other memory-mapped devices residing in the same address space is made available for SMM operations.
摘要翻译：系统管理模式对于正常的系统操作是透明的，并且动态RAM（DRAM）在上部存储器块地址范围中可用，通常在许多配置中不可访问。因此，DRAM有利地用于获得系统管理模式的读/写存储要求。系统管理模式通过在“即时”（JIT）基础上将SMM存储器切换到DRAM上部存储器块空间中，及时地将上部存储器块存储器映射的地址空间与其他非DRAM资源进行时分多路复用。 JIT操作通过在SMM输入之后锁存从CPU发出的第一个存储器地址来实现。第一个存储器地址被指定为向下延伸到存储器地址空间的存储器块的顶部地址，定义了SMM存储器范围。在SMM存储器范围内寻址的所有后续存储器访问都定向到DRAM上部存储器块，而不管通常位于与SMM存储器范围相同的地址范围内的任何其他存储器映射资源。在发生SMM恢复指令时，存储器设备映射被自动恢复到在SMM激活之前存在的配置。使用这种技术，通常用于非SMM目的的内存映射地址空间用于对系统和应用程序透明的方法中的SMM操作。有利的是，由于驻留在相同地址空间中的其他存储器映射设备的存在，可能不能正常使用的DRAM可用于SMM操作。

5. 发明授权

US06996441B1 Forward-looking fan control using system operation information 有权
标题翻译：前瞻性风扇控制使用系统操作信息
公开(公告)号：US06996441B1
公开(公告)日：2006-02-07
申请号：US10095316
申请日：2002-03-11
申请人： David F. Tobias
发明人： David F. Tobias
IPC分类号： G05B13/02
CPC分类号： G06F1/206 , G05D23/1919 , Y10S236/09
摘要： Predictions may be made regarding heat removal requirements depending on certain operational characteristics of an information processing system which have been monitored over time. A fan may be controlled based on the observed operational characteristics and based on the predictions made regarding the heat removal requirements for the system. For example, system utilization by applications may be monitored, possibly along with system performance parameters such as power level and frequency. These and other operational characteristics may be used to predict heat generation so that a fan may be controlled to anticipate temperature changes and thereby flatten temperature curves over time. This may be done in addition to monitoring the ambient temperature of the system and reacting to temperature spikes that may have already occurred.
摘要翻译：可以根据随时间监视的信息处理系统的某些操作特性来预测排热要求。可以基于观察到的操作特性并基于关于系统的散热要求的预测来控制风扇。例如，可以监视应用的系统利用率，可能与系统性能参数（例如功率电平和频率）一起被监视。可以使用这些和其它操作特性来预测发热，从而可以控制风扇以预期温度变化，从而使温度随时间变化。除了监测系统的环境温度和对可能已经发生的温度峰值作出反应之外，还可以进行此操作。

6. 发明授权

US06928586B1 Method and apparatus for saving peripheral device states of a microcontroller 失效
标题翻译：用于节省微控制器的外围设备状态的方法和装置
公开(公告)号：US06928586B1
公开(公告)日：2005-08-09
申请号：US10106631
申请日：2002-03-26
申请人： David F. Tobias , Richard G. Russell , Mark T. Ellis
发明人： David F. Tobias , Richard G. Russell , Mark T. Ellis
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318555
摘要： A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the scan path. When commanded, data is shifted out of each device configuration register onto the scan path and stored in the external memory device. This is particularly useful for obtaining the states of each device without bringing down the application. Furthermore, configuration data stored in external memory can be loaded into the peripheral device configuration registers via the scan path. This invention also supports zero-volt suspend/resume which does not need extra software readable shadow registers which are often required in other architectures for reading back the current state of legacy registers which are read-only.
摘要翻译：微控制器具有许多内部外围设备。外围设备耦合到扫描路径。在微控制器外部的存储器存储设备也耦合到扫描路径。当命令时，将数据从每个设备配置寄存器移出到扫描路径上并存储在外部存储器件中。这对于获得每个设备的状态而不会导致应用程序特别有用。此外，存储在外部存储器中的配置数据可以经由扫描路径被加载到外围设备配置寄存器中。本发明还支持零伏暂停/恢复，其不需要额外的软件可读影子寄存器，其在其他体系结构中通常需要用于读回只读只读寄存器的当前状态。

7. 发明授权

US06477482B1 Power button controlled diagnostic mode for an information appliance 有权
标题翻译：用于信息设备的电源按钮控制诊断模式
公开(公告)号：US06477482B1
公开(公告)日：2002-11-05
申请号：US09542745
申请日：2000-04-04
申请人： Patrick E. Maupin , David F. Tobias
发明人： Patrick E. Maupin , David F. Tobias
IPC分类号： G06F1310
CPC分类号： G06F11/2284
摘要： A system adds functionality to a power button where use of the power button controls the entry and exit from a diagnostic mode. The system includes an information appliance connected to a diagnostic appliance. Once an information appliance is powered up, the information appliance monitors its power button for a press which indicates a request to enter a diagnostic mode. Absent a press of the power button, the system continues to be under control of the information appliance and never enters a diagnostic mode. However, if a press of the power button is detected, the system enters a diagnostic mode. Once in a diagnostic mode the system provides an exit therefrom by interpreting a power button press as a request to exit. The window of time to make such an exit closes once the diagnostic appliance achieves communication with the information appliance. If the power button is pressed during this window of time, then the system ends its diagnostic mode and control of the system returns to the information appliance. If the power button is pressed after the window of time has closed, then the diagnostic appliance retains control of the information appliance and maintains its ability to execute diagnostic type commands thereon. The illustrative system is particularly useful when incorporated into devices with limited interface connections such as legacy-free information appliances. The system allows for a standard existing button on the information appliance to serve diagnostic purposes, avoiding the need for initializing peripherals requiring substantial execution space.
摘要翻译：系统将功能添加到电源按钮，使用电源按钮控制进入并退出诊断模式。该系统包括连接到诊断设备的信息设备。一旦信息设备通电，信息设备就会监视其按钮的电源按钮，指示进入诊断模式的请求。没有按下电源按钮，系统继续受到信息设备的控制，并且不会进入诊断模式。但是，如果检测到按下电源按钮，系统进入诊断模式。一旦进入诊断模式，系统通过解释电源按钮按钮作为退出请求来提供退出。一旦诊断设备实现与信息设备的通信，进行此类退出的时间窗口就会关闭。如果在此窗口内按下电源按钮，系统将结束其诊断模式，系统的控制返回到信息设备。如果在时间窗口关闭后按下电源按钮，则诊断设备保持对信息设备的控制，并保持其在其上执行诊断类型命令的能力。当被并入具有有限接口连接的设备（例如无遗留信息设备）中时，说明性系统特别有用。该系统允许信息设备上的标准现有按钮用于诊断目的，避免需要初始化需要大量执行空间的外设。

8. 发明授权

US07747881B2 System and method for limiting processor performance 有权
标题翻译：限制处理器性能的系统和方法
公开(公告)号：US07747881B2
公开(公告)日：2010-06-29
申请号：US11503700
申请日：2006-08-14
申请人： Francisco L. Duran , W. Paul Montgomery , David F. Tobias
发明人： Francisco L. Duran , W. Paul Montgomery , David F. Tobias
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.
摘要翻译：一种用于管理处理器的性能状态的系统和方法。外壳包括具有处理器的第一处理板和具有处理器的第二处理板。服务处理器还可以经由互连耦合到外壳。第二处理板被配置为存储指示第二板上的处理器的最大处理器性能状态的值。响应于检测到的转换到第一处理器性能状态的请求，如果第一处理器状态小于或等于最大处理器性能状态，则第二板上的处理器被配置为转换到第一处理器性能状态; 并且如果第一处理器状态大于最大处理器状态，则转换到最大处理器性能状态。第二处理器板可以响应于在外壳内的别处检测到的操作环境条件来存储该值。

9. 发明授权

US07647513B2 Method and apparatus for improving responsiveness of a power management system in a computing device 有权
标题翻译：用于提高计算设备中的电源管理系统的响应性的方法和装置
公开(公告)号：US07647513B2
公开(公告)日：2010-01-12
申请号：US11773144
申请日：2007-07-03
申请人： David F. Tobias , Evandro Menezes , Richard Russell , Morrie Altmejd
发明人： David F. Tobias , Evandro Menezes , Richard Russell , Morrie Altmejd
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.
摘要翻译：计算机系统具有多个性能状态。计算机系统周期性地确定计算机系统的利用信息，并根据利用信息调整性能状态。如果需要性能提高，则计算机系统将始终处于最大性能状态。如果需要性能下降，则计算机系统将性能状态降低到下一个较低的性能状态。

10. 发明授权

US06795927B1 Power state resynchronization 失效
标题翻译：电源状态重新同步
公开(公告)号：US06795927B1
公开(公告)日：2004-09-21
申请号：US09907083
申请日：2001-07-17
申请人： Morrie Altmejd , Richard Russell , Evandro Menezes , David F. Tobias
发明人： Morrie Altmejd , Richard Russell , Evandro Menezes , David F. Tobias
IPC分类号： G06F126
CPC分类号： G06F1/3203
摘要： A computer system has multiple performance states. The computer system periodically determines if the software power state maintained by power management software that represents the power state of the processor or other computer system component matches the actual power state of the processor or other computer system component. If not, the actual power state and the software power state are resynchronized, for example, by reinitializing the power management software or otherwise causing the software power state to match the hardware power state.
摘要翻译：计算机系统具有多个性能状态。计算机系统周期性地确定由代表处理器或其他计算机系统组件的电源状态的电源管理软件维护的软件电源状态是否与处理器或其他计算机系统组件的实际电源状态相匹配。如果没有，则例如通过重新初始化电源管理软件或以其他方式使软件电源状态与硬件电源状态相匹配来重新同步实际电源状态和软件电源状态。

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