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1. 发明申请

US20080040622A1 System and method for limiting processor performance 有权
标题翻译：限制处理器性能的系统和方法
公开(公告)号：US20080040622A1
公开(公告)日：2008-02-14
申请号：US11503700
申请日：2006-08-14
申请人： Francisco L. Duran , W. Paul Montgomery , David F. Tobias
发明人： Francisco L. Duran , W. Paul Montgomery , David F. Tobias
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.
摘要翻译：一种用于管理处理器的性能状态的系统和方法。外壳包括具有处理器的第一处理板和具有处理器的第二处理板。服务处理器还可以经由互连耦合到外壳。第二处理板被配置为存储指示第二板上的处理器的最大处理器性能状态的值。响应于检测到的转换到第一处理器性能状态的请求，如果第一处理器状态小于或等于最大处理器性能状态，则第二板上的处理器被配置为转换到第一处理器性能状态; 并且如果第一处理器状态大于最大处理器状态，则转换到最大处理器性能状态。第二处理器板可以响应于在外壳内的别处检测到的操作环境条件来存储该值。

2. 发明授权

US07747881B2 System and method for limiting processor performance 有权
标题翻译：限制处理器性能的系统和方法
公开(公告)号：US07747881B2
公开(公告)日：2010-06-29
申请号：US11503700
申请日：2006-08-14
申请人： Francisco L. Duran , W. Paul Montgomery , David F. Tobias
发明人： Francisco L. Duran , W. Paul Montgomery , David F. Tobias
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.
摘要翻译：一种用于管理处理器的性能状态的系统和方法。外壳包括具有处理器的第一处理板和具有处理器的第二处理板。服务处理器还可以经由互连耦合到外壳。第二处理板被配置为存储指示第二板上的处理器的最大处理器性能状态的值。响应于检测到的转换到第一处理器性能状态的请求，如果第一处理器状态小于或等于最大处理器性能状态，则第二板上的处理器被配置为转换到第一处理器性能状态; 并且如果第一处理器状态大于最大处理器状态，则转换到最大处理器性能状态。第二处理器板可以响应于在外壳内的别处检测到的操作环境条件来存储该值。

3. 发明授权

US07035954B1 Automatic bus speed and mode balancing after hot-plug events on hot-plug driver 有权
标题翻译：自动总线速度和热插拔事件后的模式平衡热插拔驱动程序
公开(公告)号：US07035954B1
公开(公告)日：2006-04-25
申请号：US10407092
申请日：2003-04-03
申请人： Francisco L. Duran
发明人： Francisco L. Duran
IPC分类号： H05K7/10 , G06F13/00
CPC分类号： G06F13/4081
摘要： A technique for rebalancing performance levels of one or more add-in cards is presented. Rebalancing occurs whenever a hot-plug event occurs and a change in status of a mismatch condition occurs. For example, if an add-in card is inserted that is unable to operate at the current performance level, rebalancing of the performance level occurs. Thus, for an insertion event, the performance level of all cards may be lowered. Alternatively, if an add-in card is removed and a mismatch is resolved, rebalancing of the performance level occurs. Thus, for a removal event, the performance level may be increased. The rebalancing includes disabling any enabled cards and enabling all cards at a different performance level. In one embodiment, the cards are sorted according to highest performance level available and enabled in an order of lowest to highest of the highest performance level available.
摘要翻译：提出了一种用于重新平衡一个或多个附加卡的性能水平的技术。每当发生热插拔事件并发生不匹配条件的状态改变时，就会发生再平衡。例如，如果插入无法在当前性能级别运行的附加卡，则会发生性能级别的再平衡。因此，对于插入事件，可以降低所有卡的性能水平。或者，如果删除附加卡并且不匹配，则会发生性能级别的再平衡。因此，对于删除事件，可以增加性能级别。重新平衡包括禁用任何已启用的卡，并启用不同性能级别的所有卡。在一个实施例中，根据可用的最高性能级别对卡进行排序，并以可用的最高性能级别的最低到最高的顺序启用。

4. 发明申请

US20130159750A1 METHOD AND APPARATUS FOR TRANSITIONING A SYSTEM TO AN ACTIVE DISCONNECT STATE 有权
标题翻译：将系统过渡到活动断开状态的方法和装置
公开(公告)号：US20130159750A1
公开(公告)日：2013-06-20
申请号：US13332280
申请日：2011-12-20
申请人： Alexander J. Branover , Krishna S. Bernucho , Maurice B. Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L. Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P. Shimizu , Gary H. Simpson , Laura M. Smith
发明人： Alexander J. Branover , Krishna S. Bernucho , Maurice B. Steinman , Ming L. So , Mom-Eng Ng , Xiaogang Zheng , Paul Blinzer , Francisco L. Duran , Walter G. Fry , Ali Ibrahim , Andrew W. Lueck , Dan P. Shimizu , Gary H. Simpson , Laura M. Smith
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3206
摘要： A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.
摘要翻译：处理器包括处理器核心和功率管理控制器，其可操作以接收定时器事件，存储定时器事件，生成硬件系统睡眠命令以进入硬件系统睡眠状态，以及在退出硬件系统睡眠状态时恢复定时器事件。

5. 发明授权

US6084573A Multiple mode analog joystick interface 失效
标题翻译：多模式模拟操纵杆接口
公开(公告)号：US6084573A
公开(公告)日：2000-07-04
申请号：US39283
申请日：1998-03-12
申请人： Winston Tsai , Francisco L. Duran , Seng-Khoon Tng
发明人： Winston Tsai , Francisco L. Duran , Seng-Khoon Tng
IPC分类号： G06F3/038 , G09G5/08
CPC分类号： G06F3/038 , G06F3/0383
摘要： An analog joystick interface system for overcoming the deficiencies of the conventional analog joystick interface by supporting positional tracking in both a legacy and an enhanced mode. In the legacy mode, the host calculates the relative physical orientation of a positional grip of an analog joystick by relying upon continuous polling techniques. In the enhanced mode, a watch dog timer relieves the host of the need to continuously poll by directly providing the host with positional data concerning the relative physical orientation of the positional grip. The ability of the joystick interface to provide both the legacy and enhanced modes ensures that compability issues concerning the legacy DOS-based software applications and CPU allocation problems associated with continuous polling are resolved without considerably increasing cost or complexity of the joystick interface.
摘要翻译：一种用于通过支持传统和增强模式中的位置跟踪来克服常规模拟操纵杆接口的不足的模拟操纵杆接口系统。在传统模式中，主机通过依靠连续轮询技术来计算模拟操纵杆的位置抓地力的相对物理方位。在增强模式中，看门狗定时器通过直接向主机提供关于位置握柄的相对物理取向的位置数据来消除主机的持续轮询的需要。操纵杆界面提供传统和增强模式的能力确保了解决与传统基于DOS的软件应用程序和连续轮询相关联的CPU分配问题的可兼容性问题，而不会大大增加操纵杆界面的成本或复杂性。

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