专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5517521A Method and apparatus for synchronization between real-time sampled audio applications operating full-duplex over a half-duplex radio link 失效
公开(公告)号：US5517521A
公开(公告)日：1996-05-14
申请号：US81939
申请日：1993-06-25
申请人： David F. Strawn
发明人： David F. Strawn
IPC分类号： H03L7/099 , H04B1/38 , H04B7/26 , H04J3/06 , H04L7/02 , H04L7/033
CPC分类号： H04L7/02 , H04B1/38 , H04J3/0676 , H03L7/0993 , H04J3/0697 , H04L7/0331
摘要： A method and apparatus for synchronization between an originating node and an answering node. Given the fact that it is impossible to expect that independent time bases at the originate and answer node will oscillate at exactly the same frequency, the time base at the answer node is constrained to maintain an average frequency which is identical to that established by the originate node. The answer node monitors the status of a buffer in respect of almost-full and almost-empty conditions. A binary timing control signal is generated which switches to one state in response to an almost-fill condition and switches to an opposite state in response to an almost-empty condition. When the buffer is in an almost-full state, the operating clock at the answer node is controlled so as to be slightly higher than the frequency established by the originate node. In this way, a buffer which is in an almost-full state will tend to be emptied more rapidly (by the answer node's clock) than it is filled from the originate node. On the other hand, when the buffer is in an almost-empty state, the operating clock (of the answer node) is controlled so as to be slightly lower than the clock established at the originate node. In this way, the answer node buffer will be emptied more slowly than it is being filled from the originate node. Since both nodes must actually be capable of both originate functions and answer functions, the clock at each is capable of operating at three different frequencies, the center frequency corresponding to originate node operation and the higher and lower frequencies are used in answer node operations. In a preferred embodiment, the pulse train output from an oscillator is subjected to deletion of a smaller or larger number of pulses-per-unit time. The high frequency operation (at an answer node) uses the unmodified pulse train from the oscillator. Originate node functions use the pulse train output from the oscillator which is processed by deleting a first number of pulses-per-unit time. The lower frequency operation (at an answer node) is implemented by processing the pulse train from an oscillator by deleting a larger number of pulses-per-unit time.

2. 发明授权

US5012489A Method for sending a plurality of data channels over a single communications line 失效
标题翻译：用于在单个通信线路上发送多个数据信道的方法
公开(公告)号：US5012489A
公开(公告)日：1991-04-30
申请号：US267963
申请日：1988-11-07
申请人： Richard J. Burton , John A. Copeland, III , John W. Jerrim , Toby L. Nixon , Martin H. Sauser, Jr. , Robert E. Weatherford, Jr. , Larry D. Becker , David F. Strawn
发明人： Richard J. Burton , John A. Copeland, III , John W. Jerrim , Toby L. Nixon , Martin H. Sauser, Jr. , Robert E. Weatherford, Jr. , Larry D. Becker , David F. Strawn
IPC分类号： H04L29/04 , H04L29/06
CPC分类号： H04L29/06
摘要： A method for communicating with a plurality of hosts connected to an X.25 network and for selectably using a character as a control character or a data character. Each character received from the X.25 network is inspected to determine if it is one of a set of reserved characters. If so, the character is encoded before being sent to its final destination. Data intended for the X.25 network is inspected for the presence of a predetermined control character. If the control character is present, the next character is inspected to determine whether it is a command character or an encoded data character. If this next character is an encoded data character, it is decoded and provided to the X.25 network. If this next character is a command character, then the command is executed. The method allows the use of any character as either a command character or data character. Data transfer between the DTE and DCE is assigned a PAD and a virtual channel number which corresponds to a particular host on the X.25 network. The channel number may, but need not, be the same as the X.25 device address for that host. The method therefore allows the DTE and DCE to simultaneously communicate with a plurality of X.25 hosts over a single telephone line or physical transmission link.

3. 发明授权

US4894847A High speed half duplex modem with fast turnaround protocol 失效
标题翻译：高速半双工调制解调器，具有快速周转协议
公开(公告)号：US4894847A
公开(公告)日：1990-01-16
申请号：US54419
申请日：1987-05-26
申请人： Taruna Tjahjadi , German E. Correa , Matthew F. Easley , John N. Martin , Charles H. McCorvey, Jr. , Randy D. Nash , Cynthia A. Panella , Michael L. Rubinstein , Martin H. Sauser, Jr. , David F. Strawn , George R. Thomas
发明人： Taruna Tjahjadi , German E. Correa , Matthew F. Easley , John N. Martin , Charles H. McCorvey, Jr. , Randy D. Nash , Cynthia A. Panella , Michael L. Rubinstein , Martin H. Sauser, Jr. , David F. Strawn , George R. Thomas
IPC分类号： H04L29/08 , H04L5/18 , H04L25/03 , H04M11/06
CPC分类号： H04M11/06 , H04L25/03044 , H04L5/18
摘要： A modem with improved signal processing and handshaking capabilities as described. Two digital signal processors are used to perform independent, concurrent operations so that a faster execution rate is obtained and more precise calculations are made possible. The modem also uses an improved handshaking technique which allows the modem to maintain compatibility with existing 1200 and 2400 bps modems while allowing for negotiation for 4800 and 9600 bps communications. The modem also incorporates an improved baud clock recovery circuit which dynamically adjusts the actual sampling point in a manner dependent upon the difference between the actual sampling point and the optimal sampling point. This allows the actual sampling point to converge upon the desired sampling point at a high rate while minimizing jitter around the optimal sampling point.

4. 发明授权

US5448507A Reduced logic correlator 失效
标题翻译：减少逻辑相关器
公开(公告)号：US5448507A
公开(公告)日：1995-09-05
申请号：US84978
申请日：1993-06-25
申请人： David F. Strawn
发明人： David F. Strawn
IPC分类号： G06F17/15 , H03H17/02 , G06F15/336 , G06F15/31
CPC分类号： G06F17/15 , H03H17/0254
摘要： An improved correlator or matched filter for binary coefficients is provided which reduces the amount of logic required to indicate the receipt of a predetermined code word. The matched filter includes a plurality of stages of delay, where the number of stages in the delay is preferably equal to the product of the number of chips in the code word and the number of times each chip is sampled. Logic input locations are selected corresponding to transitions in the code word. Digital logic responds to signals available at each logic input for generating data indicating the change in the degree of match between the received signal samples and the code word. An integrator is the last element in the logic and is provided with the foregoing change information. The output of the integrator is then an indication of the degree of match between the most recent set of signal transitions corresponding to the number of transitions in the sampled code word and the code word itself.
摘要翻译：提供了用于二进制系数的改进的相关器或匹配滤波器，其减少了指示预定码字的接收所需的逻辑量。匹配滤波器包括多个延迟级，其中延迟中的级数优选地等于码字中的码片数与每个码片被采样的次数的乘积。对应于代码字中的转换选择逻辑输入位置。数字逻辑响应每个逻辑输入处可用的信号，用于产生指示接收信号采样和码字之间的匹配程度变化的数据。积分器是逻辑中的最后一个元素，并且具有上述变化信息。然后，积分器的输出是对应于采样码字和码字本身中的转换次数的最近一组信号转换的匹配程度的指示。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式