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1. 发明授权

US08369433B2 Digital up-converter and N-channel modulator with flexible association of QAM generation resources to narrowcast and broadcast frequencies 有权
公开(公告)号：US08369433B2
公开(公告)日：2013-02-05
申请号：US12986772
申请日：2011-01-07
申请人： Joel I. Danzig , Richard S. Prodan , Niki Pantelias , Thomas Kolze , Victor T. Hou , Taruna Tjahjadi
发明人： Joel I. Danzig , Richard S. Prodan , Niki Pantelias , Thomas Kolze , Victor T. Hou , Taruna Tjahjadi
IPC分类号： H04K1/10 , H04L27/28
CPC分类号： H04N5/40 , H04L5/06 , H04L25/03006 , H04L27/36
摘要： Embodiments of a digital up-converter and an N-channel modulator are provided herein. The embodiments of the digital up-converter, in combination with the N-channel modulator, are capable of efficiently filling the spectrum of one or more RF signals with one or more types of information signals. For example, the digital up-converter can fill the spectrum of one or more RF signals with both broadcast and narrowcast video and data signals. In addition, the digital up-converter is capable of flexibly mapping the information signals to one or more channels of the one or more RF signals using a novel, three-level switching architecture.

2. 发明授权

US5040194A Method and apparatus for providing for automatic gain control of incoming signals in a modem 失效
标题翻译：用于在调制解调器中提供输入信号的自动增益控制的方法和装置
公开(公告)号：US5040194A
公开(公告)日：1991-08-13
申请号：US309209
申请日：1989-02-09
申请人： Taruna Tjahjadi , Randy D. Nash
发明人： Taruna Tjahjadi , Randy D. Nash
IPC分类号： H04J3/06 , H04L7/033 , H04L27/00 , H04L27/08 , H04L27/20 , H04L27/36 , H04L29/06
CPC分类号： H04L27/00 , H04J3/0605 , H04L27/08 , H04L27/2071 , H04L27/362 , H04L29/06 , H04L7/033 , H04L7/0334 , H04L7/0331
摘要： An improved circuit for providing automatic gain control (AGC) for incoming phase shift keyed (PSK) and quadrature amplitude modulated (QAM) signals. An absolute value circuit (193) and a comparator (195) provide a first error signal (197). An integrater (200,202) smoothes the first error signal (197) to provide a second error signal (201) to a variable-threshold threshold detector (204). The threshold (209) is initially set at a low value to allow the AGC circuit to quickly respond. A larger value is then used to reduce susceptibility to noise and provide for proper QAM operation. An error circuit (208,211,213) provides a non-linear response so that the gain variations will be small when the input signal (190) is large. This non-linear response further reduces the effects of noise on the AGC circuit.
摘要翻译：一种用于提供输入相移键控（PSK）和正交调幅（QAM）信号的自动增益控制（AGC）的改进电路。绝对值电路（193）和比较器（195）提供第一误差信号（197）。积分器（200,202）平滑第一误差信号（197）以向可变阈值阈值检测器（204）提供第二误差信号（201）。阈值（209）最初被设置为低值以允许AGC电路快速响应。然后使用较大的值来降低对噪声的敏感性并提供适当的QAM操作。误差电路（208,211,213）提供非线性响应，使得当输入信号（190）较大时，增益变化将较小。该非线性响应进一步降低了噪声对AGC电路的影响。

3. 发明授权

US4894847A High speed half duplex modem with fast turnaround protocol 失效
标题翻译：高速半双工调制解调器，具有快速周转协议
公开(公告)号：US4894847A
公开(公告)日：1990-01-16
申请号：US54419
申请日：1987-05-26
申请人： Taruna Tjahjadi , German E. Correa , Matthew F. Easley , John N. Martin , Charles H. McCorvey, Jr. , Randy D. Nash , Cynthia A. Panella , Michael L. Rubinstein , Martin H. Sauser, Jr. , David F. Strawn , George R. Thomas
发明人： Taruna Tjahjadi , German E. Correa , Matthew F. Easley , John N. Martin , Charles H. McCorvey, Jr. , Randy D. Nash , Cynthia A. Panella , Michael L. Rubinstein , Martin H. Sauser, Jr. , David F. Strawn , George R. Thomas
IPC分类号： H04L29/08 , H04L5/18 , H04L25/03 , H04M11/06
CPC分类号： H04M11/06 , H04L25/03044 , H04L5/18
摘要： A modem with improved signal processing and handshaking capabilities as described. Two digital signal processors are used to perform independent, concurrent operations so that a faster execution rate is obtained and more precise calculations are made possible. The modem also uses an improved handshaking technique which allows the modem to maintain compatibility with existing 1200 and 2400 bps modems while allowing for negotiation for 4800 and 9600 bps communications. The modem also incorporates an improved baud clock recovery circuit which dynamically adjusts the actual sampling point in a manner dependent upon the difference between the actual sampling point and the optimal sampling point. This allows the actual sampling point to converge upon the desired sampling point at a high rate while minimizing jitter around the optimal sampling point.

4. 发明授权

US07474713B2 System and method for demodulating multiple QAM signals 有权
标题翻译：用于解调多个QAM信号的系统和方法
公开(公告)号：US07474713B2
公开(公告)日：2009-01-06
申请号：US11197262
申请日：2005-08-05
申请人： Taruna Tjahjadi
发明人： Taruna Tjahjadi
IPC分类号： H04L27/22 , H03K9/00 , H03D1/00 , H03D3/00
CPC分类号： H04L27/38 , H04L27/2653
摘要： A system and method demodulate N QAM signals (N being a positive integer equal to or greater than 1) substantially simultaneously using, for example, one or two oscillators, regardless of how many QAM signals need to be demodulated.
摘要翻译：基本上同时使用例如一个或两个振荡器的N个QAM信号（N等于或大于1的正整数）的系统和方法，而不管需要解调多少个QAM信号。

5. 发明授权

US5040192A Method and apparatus for optimally autocorrelating an FSK signal 失效
标题翻译：用于最佳地自相关FSK信号的方法和装置
公开(公告)号：US5040192A
公开(公告)日：1991-08-13
申请号：US475940
申请日：1990-02-06
申请人： Taruna Tjahjadi
发明人： Taruna Tjahjadi
IPC分类号： H04L7/02 , H04L27/152
CPC分类号： H04L27/1525 , H04L7/0029
摘要： An autocorrelator for FSK signals. An FSK signal, incoming on a telephone line is filtered by a bandpass filter (13) and sampled by an A/D converter (14). A sample clock (15) provides a fixed sampling frequency, FS. A first interpolating filter (20B) provides selectable delays which are non-integer multiples of 1/FS, and an integer delay (25) provides selectable delays which are integer multiples of 1/FS. The delayed signals are multiplied by a multiplier (26) and then filtered by a low pass filter (27) to provide a filtered autocorrelated signal. A second interpolating filter (20A) provides for reduced jitter in the baud timing by increasing the number of samples provided to the decision logic (23). The decision logic (23) provides the decoded data output.
摘要翻译：用于FSK信号的自相关器。由电话线路进入的FSK信号由带通滤波器（13）滤波并由A / D转换器（14）采样。采样时钟（15）提供固定的采样频率FS。第一内插滤波器（20B）提供作为1 / FS的非整数倍的可选延迟，并且整数延迟（25）提供作为1 / FS的整数倍的可选延迟。延迟信号乘以乘法器（26），然后由低通滤波器（27）滤波，以提供滤波的自相关信号。第二内插滤波器（20A）通过增加提供给判定逻辑（23）的采样数量来提供波特率定时中的抖动减小。判定逻辑（23）提供解码数据输出。

6. 发明授权

US5001729A High speed half duplex modem with fast turnaround protocol 失效
标题翻译：高速半双工调制解调器，具有快速周转协议
公开(公告)号：US5001729A
公开(公告)日：1991-03-19
申请号：US381142
申请日：1989-07-17
申请人： Taruna Tjahjadi , Matthew F. Easley , Randy D. Nash
发明人： Taruna Tjahjadi , Matthew F. Easley , Randy D. Nash
IPC分类号： H04L5/18 , H04L25/03 , H04M11/06
CPC分类号： H04M11/06 , H04L25/03044 , H04L5/18
摘要： A phase locked loop circuit which eliminates the phase difference between an incoming reference signal and a sampling signal by sampling the incoming reference signal to produce a sampled signal. The sign of the sampled signal at two sample points is compared to determine in which quadrant a predetermined one of these sample points is located. The phase adjustment to the sampling signal is dependent upon the quadrant in which this sample point is located and the magnitude of this sample point. A large phase difference produces a large phase adjustment so that this sample point is quickly locked onto the zero-crossing points of the incoming reference signal. A small phase difference produces a small phase adjustment and prevents jitter. The lock onto the zero-crossing point of the incoming reference signal minimizes the data error rate of the modem.
摘要翻译：一种锁相环电路，通过对输入的参考信号进行采样以产生采样信号来消除输入参考信号和采样信号之间的相位差。比较两个采样点的采样信号的符号，以确定这些采样点中的预定一个位于哪个象限中。对采样信号的相位调整取决于该采样点所在的象限和该采样点的幅度。大的相位差产生大的相位调整，使得该采样点被快速锁定到输入参考信号的过零点上。小的相位差产生小的相位调整并防止抖动。进入参考信号的过零点锁定将调制解调器的数据错误率最小化。

7. 发明申请

US20110170632A1 Digital Up-Converter and N-Channel Modulator With Flexible Association of QAM Generation Resources to Narrowcast and Broadcast Frequencies 有权
标题翻译：数字上变频器和N通道调制器，具有灵活的QAM生成资源关联到窄播和广播频率
公开(公告)号：US20110170632A1
公开(公告)日：2011-07-14
申请号：US12986772
申请日：2011-01-07
申请人： Joel I. Danzig , Richard S. Prodan , Niki Pantelias , Thomas Kolze , Victor T. Hou , Taruna Tjahjadi
发明人： Joel I. Danzig , Richard S. Prodan , Niki Pantelias , Thomas Kolze , Victor T. Hou , Taruna Tjahjadi
IPC分类号： H04L27/36 , H04L25/03
CPC分类号： H04N5/40 , H04L5/06 , H04L25/03006 , H04L27/36
摘要： Embodiments of a digital up-converter and an N-channel modulator are provided herein. The embodiments of the digital up-converter, in combination with the N-channel modulator, are capable of efficiently filling the spectrum of one or more RF signals with one or more types of information signals. For example, the digital up-converter can fill the spectrum of one or more RF signals with both broadcast and narrowcast video and data signals. In addition, the digital up-converter is capable of flexibly mapping the information signals to one or more channels of the one or more RF signals using a novel, three-level switching architecture.
摘要翻译：本文提供数字上变频器和N沟道调制器的实施例。数字上变频器与N信道调制器结合的实施例能够利用一种或多种类型的信息信号有效地填充一个或多个RF信号的频谱。例如，数字上变频器可以用广播和窄视频和数据信号来填充一个或多个RF信号的频谱。此外，数字上变频器能够使用新颖的三电平交换架构将信息信号灵活地映射到一个或多个RF信号的一个或多个信道。

8. 发明申请

US20070030916A1 System and method for demodulating multiple QAM signals 有权
标题翻译：用于解调多个QAM信号的系统和方法
公开(公告)号：US20070030916A1
公开(公告)日：2007-02-08
申请号：US11197262
申请日：2005-08-05
申请人： Taruna Tjahjadi
发明人： Taruna Tjahjadi
IPC分类号： H04L5/12 , H04L27/00
CPC分类号： H04L27/38 , H04L27/2653
摘要： A system and method demodulate N QAM signals (N being a positive integer equal to or greater than 1) substantially simultaneously using, for example, one or two oscillators, regardless of how many QAM signals need to be demodulated.
摘要翻译：基本上同时使用例如一个或两个振荡器的N个QAM信号（N等于或大于1的正整数）的系统和方法，而不管需要解调多少个QAM信号。

9. 发明授权

US5070514A Method and apparatus for clearing data path in half duplex modem receiver while maintaining dynamic parameters 失效
标题翻译：在保持动态参数的同时，在半双工调制解调器接收机中清除数据路径的方法和装置
公开(公告)号：US5070514A
公开(公告)日：1991-12-03
申请号：US454180
申请日：1989-12-21
申请人： Taruna Tjahjadi
发明人： Taruna Tjahjadi
IPC分类号： H04L5/16 , H04M11/06
CPC分类号： H04M11/06 , H04L5/16
摘要： A DSP receiver for a fast turnaround modem, particularly suited for a half duplex fast turnaround modem which prevents destruction of communication channel related adaptive equalizer parameters upon loss of carrier. Upon detection of carrier loss, after sufficient time has been allowed for the last informational data bits to pass through the receiver's adaptive equalizer, the output of the equalizer's FIR filter delay line is looped back, via a multiplexer, to the input of the equalizer so that communications channel related samples are continuously provided to the equalizer to maintain the parameters at values based on the receiver's actual experience with data transmitted through the communications channel to which it is connected. A delay timer responsive to the loss of carrier signal will terminate updating of the adaptive equalizer parameters a predetermined time after loss of carrier. Alternately, detection of a standard end of data flag in the data stream will also terminate parameter update.
摘要翻译：用于快速周转调制解调器的DSP接收器，特别适用于半双工快速周转调制解调器，防止在丢失载波时破坏通信信道相关的自适应均衡器参数。在检测到载波丢失时，在允许最后信息数据位通过接收机的自适应均衡器足够的时间之后，均衡器的FIR滤波器延迟线的输出通过多路复用器被环回到均衡器的输入端该通信信道相关样本被连续地提供给均衡器，以便基于接收机的实际体验将参数维持在通过与其连接的通信信道发送的数据的值。响应于载波信号丢失的延迟定时器将在丢失载波之后的预定时间内终止自适应均衡器参数的更新。或者，数据流中标准数据标志结束的检测也将终止参数更新。

10. 发明授权

US4849703A Method and apparatus for generating a data sampling clock locked to a baud clock contained in a data signal 失效
标题翻译：用于产生锁定在包含在数据信号中的波特率时钟的数据采样时钟的方法和装置
公开(公告)号：US4849703A
公开(公告)日：1989-07-18
申请号：US176692
申请日：1988-04-01
申请人： Matthew F. Easley , German E. Correa , Randy D. Nash , Cynthia A. Panella , Taruna Tjahjadi
发明人： Matthew F. Easley , German E. Correa , Randy D. Nash , Cynthia A. Panella , Taruna Tjahjadi
IPC分类号： H04J3/06 , H04L7/033 , H04L27/00 , H04L27/08 , H04L27/20 , H04L27/36 , H04L29/06
CPC分类号： H04L7/0334 , H04J3/0605 , H04L27/00 , H04L27/08 , H04L27/2071 , H04L27/362 , H04L29/06 , H04L7/0331
摘要： An improved baud clock recovery, synchronization and data sampling circuit for a modem. A CODEC (41) samples the incoming signal at a rate determined by the sample clock output of a presettable counter (236). The sampled signal is then squared (231) and bandpass filtered (232) to provide a recovered baud clock. A detector (233) signals the positive going zero-crossing points of the recovered baud clock. A lead/lag calculator (234) determines which of the signal samples is nearest the zero-crossing point. The calculator (234) then determines whether this and every subsequent 12th sampling point leads or lags the zero-crossing point by inspecting the sign of the recovered baud clock and adjusts the preset inputs of the counter (236) to cause the sample points to occur at the zero-crossing point.
摘要翻译：改进的波特率时钟恢复，调制解调器的同步和数据采样电路。 CODEC（41）以由可预设计数器（236）的采样时钟输出确定的速率对输入信号进行采样。采样信号然后平方（231）并带通滤波（232）以提供恢复的波特率时钟。检测器（233）用信号通知恢复的波特率时钟的正向过零点。引导/延迟计算器（234）确定哪个信号采样最接近过零点。然后，计算器（234）通过检查恢复的波特率时钟的符号来确定该和每个随后的第十二采样点是否引导或滞后过零点，并调整计数器（236）的预设输入以使样本点发生在过零点。

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