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1. 发明授权

US5218683A Method and apparatus for concealing the enablement of a device by modifying a status word 失效
标题翻译：通过修改状态字来隐藏设备启用的方法和装置
公开(公告)号：US5218683A
公开(公告)日：1993-06-08
申请号：US873966
申请日：1992-04-24
申请人： John W. Jerrim , Scott C. Swanson
发明人： John W. Jerrim , Scott C. Swanson
IPC分类号： G06F13/12
CPC分类号： G06F13/126
摘要： A status word modification device. A serial communications device (11) contains two universal asynchronous receiver transmitters (UARTs) (14, 15). Each UART contains a first in, first out (FIFO) buffer (14a), two status buffers (14b, 14c), and a FIFO control register (14d). If the applications program in the host (10) is an enhanced application program which supports the use of the FIFO buffer (14a), then the program will cause FIFO enablement instructions to be written into the control register (14d). In this case, the interface circuit (22) allows the status words to pass unaltered whenever the host (10) reads the status buffers (14b, 14c). However, if the applications program is a standard applications program which does not support the use of the FIFO buffer (14a), then the program will not write to the control register (14d). In this case, the interface circuit (22) will alter the value of selected bits of the status words if the user has enabled the FIFO buffer (14a) and the host reads the status buffers (14b, 14c). The alteration of the status word prevents the standard applications program from treating the FIFO-related bits in the status words as data errors.
摘要翻译：状态字修改装置。串行通信设备（11）包含两个通用异步接收器发射器（UART）（14,15）。每个UART包含一个先进先出（FIFO）缓冲器（14a），两个状态缓冲器（14b，14c）和一个FIFO控制寄存器（14d）。如果主机（10）中的应用程序是支持使用FIFO缓冲器（14a）的增强应用程序，则程序将使FIFO启用指令被写入控制寄存器（14d）。在这种情况下，只要主机（10）读取状态缓冲器（14b，14c），接口电路（22）允许状态字通过。然而，如果应用程序是不支持使用FIFO缓冲器（14a）的标准应用程序，则程序将不会写入控制寄存器（14d）。在这种情况下，如果用户已启用FIFO缓冲器（14a）并且主机读取状态缓冲器（14b，14c），则接口电路（22）将改变状态字的选定位的值。状态字的更改可防止标准应用程序将状态字中的FIFO相关位视为数据错误。

2. 发明授权

US4567588A Synchronization system for use in direct sequence spread spectrum signal receiver 失效
标题翻译：用于直接序列扩频信号接收机的同步系统
公开(公告)号：US4567588A
公开(公告)日：1986-01-28
申请号：US592667
申请日：1984-03-23
申请人： John W. Jerrim
发明人： John W. Jerrim
IPC分类号： H04B1/707 , H04J13/00
CPC分类号： H04B1/707 , H04J13/00
摘要： A plurality of transmitters synchronized to a common clock each transmit a data signal spread by a common bipolar pseudo-random code having a different assigned code sequence shift. A receiver, synchronized to the clock, discriminates the signals transmitted by a predetermined transmitter from signals transmitted by the others by generating a first pseudo-random code that is a replica of the common bipolar pseudo-random code and has a code sequence shift corresponding to that of the predetermined transmitter, and a second bipolar pseudo-random code that is a replica of the common bipolar pseudo-random code and has an unassigned code sequence shift. The difference between the first and second bipolar pseudo-random code sequences, which is a trinary code sequence, is cross-correlated with the incoming signals. The cross-correlation despreads only the signal having the predetermined code sequence shift. Each receiver includes a number of correlation detectors offset from each other by a fraction of a code chip, together with decision circuitry to identify cross-correlation peaks. The cross-correlation output of a primary correlation detector generates in-phase and quadrature-phase correlation signals, with the quadrature-phase signal being at a minimum when the receiver and predetermined transmitter are perfectly synchronized with each other. The ratio of the in-phase and quadrature-phase signals are processed to identify the presence of a data signal within a background of noise and to improve synchronization lock between the receiver and predetermined transmitter.
摘要翻译：与公共时钟同步的多个发射机各自发送由具有不同分配码序列偏移的公共双极性伪随机码扩展的数据信号。与时钟同步的接收机通过产生作为公共双极性伪随机码的复制品的第一伪随机码来识别由预定发射机发送的信号与其他信号发送的信号，并且具有对应于以及作为公共双极性伪随机码的副本并且具有未分配的码序列移位的第二双极性伪随机码。作为三进制码序列的第一和第二双极性伪随机码序列之间的差异与输入信号相互关联。互相关仅解扩定具有预定码序列偏移的信号。每个接收机包括多个相关检测器，它们由码片的一小部分彼此偏移，以及用于识别互相关峰值的判定电路。主相位检测器的互相关输出产生同相和正交相位相关信号，当接收机和预定发射机彼此完全同步时，正交相位信号为最小。处理同相和正交相位信号的比率以识别噪声背景下的数据信号的存在并且改善接收机和预定发射机之间的同步锁定。

3. 发明授权

US4327416A Temperature compensation system for Hall effect element 失效
标题翻译：霍尔效应元件温度补偿系统
公开(公告)号：US4327416A
公开(公告)日：1982-04-27
申请号：US140954
申请日：1980-04-16
申请人： John W. Jerrim
发明人： John W. Jerrim
IPC分类号： G01R21/08 , G01R33/07 , G01R33/06
CPC分类号： G01R21/08 , G01R33/07
摘要： In a solid state current, power or energy meter having a Hall element magnetically coupled to line current, a system for compensating the Hall voltage for its dependence on temperature comprises a read only memory (ROM) containing experimentally obtained temperature compensation data. The temperature of the Hall element is measured by a thermistor to develop a temperature dependent voltage. In one embodiment, the Hall element voltage and temperature dependent voltage are digitalized and supplied to address the ROM to generate a temperature compensated Hall voltage. In a second embodiment, the ROM is addressed by only the temperature dependent voltage to generate a correction voltage that is added to the Hall element voltage for temperature compensation.
摘要翻译：在固态电流中，具有与线电流磁耦合的霍尔元件的功率或能量计包括用于补偿其与温度相关的霍尔电压的系统，其包括包含实验获得的温度补偿数据的只读存储器（ROM）。通过热敏电阻测量霍尔元件的温度，以产生与温度有关的电压。在一个实施例中，霍尔元件电压和温度相关电压被数字化并被提供以寻址ROM以产生温度补偿霍尔电压。在第二实施例中，仅通过温度依赖电压对ROM进行寻址，以产生加到霍尔元件电压进行温度补偿的校正电压。

4. 发明授权

US5012489A Method for sending a plurality of data channels over a single communications line 失效
标题翻译：用于在单个通信线路上发送多个数据信道的方法
公开(公告)号：US5012489A
公开(公告)日：1991-04-30
申请号：US267963
申请日：1988-11-07
申请人： Richard J. Burton , John A. Copeland, III , John W. Jerrim , Toby L. Nixon , Martin H. Sauser, Jr. , Robert E. Weatherford, Jr. , Larry D. Becker , David F. Strawn
发明人： Richard J. Burton , John A. Copeland, III , John W. Jerrim , Toby L. Nixon , Martin H. Sauser, Jr. , Robert E. Weatherford, Jr. , Larry D. Becker , David F. Strawn
IPC分类号： H04L29/04 , H04L29/06
CPC分类号： H04L29/06
摘要： A method for communicating with a plurality of hosts connected to an X.25 network and for selectably using a character as a control character or a data character. Each character received from the X.25 network is inspected to determine if it is one of a set of reserved characters. If so, the character is encoded before being sent to its final destination. Data intended for the X.25 network is inspected for the presence of a predetermined control character. If the control character is present, the next character is inspected to determine whether it is a command character or an encoded data character. If this next character is an encoded data character, it is decoded and provided to the X.25 network. If this next character is a command character, then the command is executed. The method allows the use of any character as either a command character or data character. Data transfer between the DTE and DCE is assigned a PAD and a virtual channel number which corresponds to a particular host on the X.25 network. The channel number may, but need not, be the same as the X.25 device address for that host. The method therefore allows the DTE and DCE to simultaneously communicate with a plurality of X.25 hosts over a single telephone line or physical transmission link.

5. 发明授权

US5179661A Method and apparatus for serial data flow control 失效
标题翻译：串行数据流控制的方法和装置
公开(公告)号：US5179661A
公开(公告)日：1993-01-12
申请号：US429065
申请日：1989-10-30
申请人： John A. Copeland, III , John W. Jerrim , Scott C. Swanson
发明人： John A. Copeland, III , John W. Jerrim , Scott C. Swanson
IPC分类号： H04L12/56 , H04L29/06
CPC分类号： H04L47/10 , H04L29/06
摘要： A data flow controller (150) for monitoring and automatically controlling the flow of serial data from a remote transmitter to a host device. A serial communications card (11) provides an interface between a remote transmitter connected to a serial port connector (20) and a host device (10). The card (11) contains a UART (14) which has a buffer. A counter (151) counts the number of bytes received by the UART (14) since the last time that the host (10) read all the data in the buffer. If the number exceeds a predetermined portion of the buffer capacity the counter output (Q11) will go high, thereby disabling the counter and sending a control signal (DTR, RTS) to the remote transmitter to stop sending data. Once the host (10) has read all the data in the buffer the UART (14) provides a signal (-RXREADY) which resets the counter (151), thereby causing the output (Q11) to go low, thereby allowing the remote transmitter to resume sending data. The counter (151) is held in a reset state until the buffer has received at least one byte of data. Data flow control is therefore obtained without the intervention of the host (10).

6. 发明授权

US4653076A Timing signal correction system for use in direct sequence spread signal receiver 失效
标题翻译：定时信号校正系统用于直接序列扩频信号接收机
公开(公告)号：US4653076A
公开(公告)日：1987-03-24
申请号：US592668
申请日：1984-03-23
申请人： John W. Jerrim , Lawrence B. Horwitz
发明人： John W. Jerrim , Lawrence B. Horwitz
IPC分类号： H04B1/707 , H04B1/7075 , H04B1/7085 , H04J13/00 , H04L7/02
CPC分类号： H04B1/7075 , H04B1/707 , H04B1/7085 , H04J13/00
摘要： A direct sequence spread spectrum transmitter and receiver can be synchronized when the timing reference frequency is less than or equal to the data sampling rate and the ratio of the data sampling rate to the timing reference is an integer by combining two, four or eight consecutive data samples to yield one data sample point. By combining these data samples, an optimum data sample point may be determined while receiving an alternating sign preamble by comparing the magnitudes of all possible summations and selecting the sample which gives a maximum output. If each sample is assigned to its own synchronization point, then synchronization may be accomplished by locking to the time that gives the maximum output.
摘要翻译：当定时参考频率小于或等于数据采样率时，直接序列扩频发射机和接收机可以同步，并且通过组合两个，四个或八个连续数据，数据采样率与定时参考的比率是整数样本产生一个数据采样点。通过组合这些数据样本，可以通过比较所有可能的求和的大小并选择给出最大输出的样本来接收交替符号前同步码来确定最佳数据采样点。如果将每个样本分配给自己的同步点，则可以通过锁定到给出最大输出的时间来实现同步。

7. 发明授权

US4335447A Power outage recovery method and apparatus for demand recorder with solid state memory 失效
标题翻译：具有固态存储器的需求记录器的停电恢复方法和装置
公开(公告)号：US4335447A
公开(公告)日：1982-06-15
申请号：US118830
申请日：1980-02-05
申请人： John W. Jerrim
发明人： John W. Jerrim
IPC分类号： G06F3/00 , G06Q30/04 , G11C11/00 , G11C7/00
CPC分类号： G06Q30/04 , G06F3/007
摘要： A demand recorder includes a microprocessor for receiving data pulses representative of measured events and formats the incoming data into demand intervals. After a predetermined number of demand intervals, called a collection period, the microprocessor transfers the data for more permanent storage to a solid state memory which may be removed for remote processing. The system has battery carryover during a power outage, but the microprocessor prevents data transfers to the solid state memory. At the end of a collection period in which a power outage occurred, the microprocessor transfers the current data to a secondary portion of random access memory. For subsequent demand intervals until power is restored and including any thermal recovery periods, the processor formats event data by assigning index numbers for demand intervals in order of occurrence and stores data only for those demand intervals in which power consumption was actually measured. After the system has returned to normal operation, the data temporarily stored in secondary RAM is transferred to the solid state memory and the data in primary RAM which is stored in compacted format is re-constructed into normal storage format in RAM with all intervals during which no event data was detected being zero-filled. As data is taken from primary RAM, converted into the original format and transferred to secondary RAM for storage in the solid state memory, the remaining data in primary RAM is advanced in memory, similar to the operation of a stack memory, so that as much space as possible is made available for data storage in the event of a subsequent power outage prior to the time all of the data in primary RAM is converted and stored in the solid state memory.
摘要翻译：需求记录器包括微处理器，用于接收表示测量事件的数据脉冲，并将输入数据格式化成需求间隔。在预定数量的需求间隔（称为收集周期）之后，微处理器将用于更多永久存储的数据传送到固态存储器，固态存储器可被移除用于远程处理。系统在停电期间具有电池遗留，但微处理器可防止数据传输到固态存储器。在发生停电的收集周期结束时，微处理器将当前数据传送到随机存取存储器的次要部分。对于随后的需求间隔，直到电力恢复并且包括任何热恢复时段，处理器通过按照发生顺序分配需求间隔的索引号来格式化事件数据，并且仅存储实际测量功耗的那些需求间隔的数据。在系统恢复正常操作之后，临时存储在二级RAM中的数据被传送到固态存储器，并且将以压缩格式存储的主RAM中的数据以所有时间间隔重新构建成RAM中的正常存储格式没有检测到事件数据为零填充。当从主RAM获取数据时，转换为原始格式并传输到二级RAM以存储在固态存储器中，主RAM中的剩余数据在存储器中进行，类似于堆栈存储器的操作，因此尽可能多在主RAM中的所有数据被转换并存储在固态存储器中之前，在随后的断电的情况下，空间可用于数据存储。

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