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1. 发明申请

WO2014081469A1 FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的灵活磨损管理
公开(公告)号：WO2014081469A1
公开(公告)日：2014-05-30
申请号：PCT/US2013/045616
申请日：2013-06-13
申请人： INTEL CORPORATION , DAMLE, Prashant , FABER, Robert , XIE, Ningde
发明人： DAMLE, Prashant , FABER, Robert , XIE, Ningde
IPC分类号： G06F12/00 , G06F13/14
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a "hot address" if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a "cold address". The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.
摘要翻译：可以实现跨存储器单元地址空间的写周期更均匀分布的存储器单元磨损管理的系统和方法。这些系统和方法允许经受大量写入周期的存储器单元的物理地址与经受较少写入周期的存储器单元的物理地址交换。如果该存储单元组的写周期计数超过指定的阈值，则一组存储单元的物理地址是“热地址”。如果一组存储单元的写周期计数不超过指定的阈值，则该存储单元组的物理地址为“冷地址”。系统和方法允许指定的写周期计数阈值动态增加，以确保冷地址可用于与存储单元地址空间中的热地址进行交换。

2. 发明申请

WO2014164099A1 REDUCED UNCORRECTABLE MEMORY ERRORS 审中-公开
标题翻译：减少不可避免的内存错误
公开(公告)号：WO2014164099A1
公开(公告)日：2014-10-09
申请号：PCT/US2014/020549
申请日：2014-03-05
申请人： INTEL CORPORATION , PANGAL, Kiran , DAMLE, Prashant S. , SUNDARAM, Rajesh , QAWAMI, Shekoufeh , WALKER, Julie M. , RIVERS, Doyle
发明人： PANGAL, Kiran , DAMLE, Prashant S. , SUNDARAM, Rajesh , QAWAMI, Shekoufeh , WALKER, Julie M. , RIVERS, Doyle
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1044 , G06F11/1048 , G06F11/1068 , H03M13/05 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27 , H03M13/6508
摘要： Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
摘要翻译：可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误的存储器阵列。然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。

3. 发明申请

WO2014051776A1 TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM 审中-公开
标题翻译：与两级存储系统的阅读和写入窗口预算相关的技术
公开(公告)号：WO2014051776A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/047453
申请日：2013-06-25
申请人： INTEL CORPORATION , PANGAL, Kiran , DAMLE, Prashant
发明人： PANGAL, Kiran , DAMLE, Prashant
IPC分类号： G06F12/02
CPC分类号： G06F11/1068 , G06F11/1008 , G06F11/1048 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C16/10 , G11C16/26
摘要： Examples are disclosed for techniques associated with a read and write window budget for a two level memory (2LM) system. In some examples, a read and write window budget may be established for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory. Other examples are described and claimed.
摘要翻译：公开了与用于二级存储器（2LM）系统的读取和写入窗口预算相关联的技术的示例。在一些示例中，可以为包括第一级存储器和第二级存储器的2LM系统建立读和写窗口预算。所建立的读写窗口预算可以包括第一组存储器地址和第二级存储器的第二组存储器地址的组合。与第二组存储器地址相关联的非易失性存储器单元的单元阈值电压分布相比，第一组存储器地址可以与具有更宽的单元阈值电压分布的非易失性存储单元相关联。根据一些示例，建立的读和写窗口预算可以是满足给定量的存储器的完成时间阈值和给定量的存储器的可接受的错误率阈值的策略的一部分，当满足对该存储器的读取或写入请求时，二级内存其他的例子被描述和要求保护。

4. 发明申请

WO2013184111A1 ISOLATING, AT LEAST IN PART, LOCAL ROW OR COLUMN CIRCUITRY OF MEMORY CELL BEFORE ESTABLISHING VOLTAGE DIFFERENTIAL TO PERMIT READING OF CELL 审中-公开
标题翻译：在建立电压差异到容许读取单元之前，至少分开存储单元的本地线或列电路
公开(公告)号：WO2013184111A1
公开(公告)日：2013-12-12
申请号：PCT/US2012/041166
申请日：2012-06-06
申请人： INTEL CORPORATION , RIVERS, Doyle , DAMLE, Prashant, S. , ZENG, Raymond, W.
发明人： RIVERS, Doyle , DAMLE, Prashant, S. , ZENG, Raymond, W.
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C7/02 , G11C13/004
摘要： An embodiment may include local row and column circuitry that are local to a memory cell of a memory device. Either the local row circuitry or the local column circuitry may be electrically isolated, at least in part, from at least one remaining portion of the memory device during the establishing of a voltage differential between the local row circuitry and the local column circuitry that is to permit the memory cell to be read during a read of the memory cell. The read may occur subsequent to the establishing of the voltage differential. Many variations, modifications, and alternatives are possible without departing from this embodiment.
摘要翻译：实施例可以包括对存储器件的存储器单元本地的本地行和列电路。在本地行电路和本地列电路之间的电压差建立期间，本地行电路或本地列电路可以至少部分地与存储器件的至少一个剩余部分电隔离，允许在存储器单元的读取期间读取存储器单元。读取可能在建立电压差之后发生。在不脱离本实施例的情况下，可以进行许多变化，修改和替换。

5. 发明申请

WO2015047334A1 ERROR CORRECTION IN NON_VOLATILE MEMORY 审中-公开
标题翻译： NON_VOLATILE MEMORY中的错误修正
公开(公告)号：WO2015047334A1
公开(公告)日：2015-04-02
申请号：PCT/US2013/062405
申请日：2013-09-27
申请人： INTEL CORPORATION , KWOK, Zion S. , MOTWANI, Ravi H. , PANGAL, Kiran , DAMLE, Prashant S.
发明人： KWOK, Zion S. , MOTWANI, Ravi H. , PANGAL, Kiran , DAMLE, Prashant S.
IPC分类号： G06F11/10 , G06F12/00
CPC分类号： G06F11/1068 , G06F11/10 , G06F11/1044 , G06F11/108 , G06F12/00 , G06F2212/7207 , G11C29/52 , H03M13/1515 , H03M13/152
摘要： Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to receive a read request for data stored in a memory, retrieve the data and at least one associated error correction codeword, wherein the data and an associated error correction codeword is distributed across a plurality of memory devices in memory, apply a first error correction routine to decode the error correction codeword retrieved with the data and in response to an uncorrectable error in the error correction codeword, apply a second error correction routine to the plurality of devices in memory. Other embodiments are also disclosed and claimed.
摘要翻译：描述了存储器中用于纠错的装置，系统和方法。在一个实施例中，存储器控制器包括接收对存储在存储器中的数据的读取请求的逻辑，检索数据和至少一个相关联的纠错码字，其中数据和相关联的纠错码字分布在多个存储器件在存储器中，应用第一纠错程序来解码用数据检索的纠错码字，并响应错误校正码字中的不可校正错误，对存储器中的多个设备应用第二纠错例程。还公开并要求保护其他实施例。

6. 发明申请

WO2010104971A1 MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION 审中-公开
标题翻译：具有改进的编程操作的存储器件
公开(公告)号：WO2010104971A1
公开(公告)日：2010-09-16
申请号：PCT/US2010/026854
申请日：2010-03-10
申请人： MICRON TECHNOLOGY, INC. , DAMLE, Prashant, S. , PARAT, Krishna , TORSI, Alessandro , MUSILLI, Carlo , VAKATI, Kalpana , GODA, Akira
发明人： DAMLE, Prashant, S. , PARAT, Krishna , TORSI, Alessandro , MUSILLI, Carlo , VAKATI, Kalpana , GODA, Akira
IPC分类号： G11C16/34 , G11C16/10 , G11C16/12 , G11C16/32
CPC分类号： G11C16/3404 , G11C16/0483 , G11C16/10 , G11C16/32
摘要： Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
摘要翻译：一些实施例包括具有模块和存储器单元的方法和装置。该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

7. 发明申请

WO2015138281A1 MITIGATING READ DISTURB IN A CROSS-POINT MEMORY 审中-公开
标题翻译：减少跨点记忆中的读取干扰
公开(公告)号：WO2015138281A1
公开(公告)日：2015-09-17
申请号：PCT/US2015/019366
申请日：2015-03-09
申请人： INTEL CORPORATION , CHU, Daniel J. , PANGAL, Kiran , FRANKLIN, Nathan R. , DAMLE, Prashant S. , CHAOHONG, Hu
发明人： CHU, Daniel J. , PANGAL, Kiran , FRANKLIN, Nathan R. , DAMLE, Prashant S. , CHAOHONG, Hu
IPC分类号： G11C13/00 , G11C7/06 , G11C7/10
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0035 , G11C13/0061 , G11C2013/0047 , G11C2013/0052
摘要： The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
摘要翻译：本公开涉及减轻交叉点存储器中的读取干扰。设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控制器。存储器控制器包括感测模块，其被配置为确定在感测间隔期间是否发生快照事件; 以及写回模块，被配置为如果检测到快照事件，则将逻辑1写回到所述存储器单元。

8. 发明申请

WO2014051775A1 TECHNIQUES ASSOCIATED WITH PROTECTING SYSTEM CRITICAL DATA WRITTEN TO NON-VOLATILE MEMORY 审中-公开
标题翻译：与保护系统相关的技术关键数据写入非易失性存储器
公开(公告)号：WO2014051775A1
公开(公告)日：2014-04-03
申请号：PCT/US2013/047442
申请日：2013-06-24
申请人： INTEL CORPORATION , PANGAL, Kiran , MOTWANI, Ravi H. , DAMLE, Prashant S.
发明人： PANGAL, Kiran , MOTWANI, Ravi H. , DAMLE, Prashant S.
IPC分类号： G06F12/16 , G06F11/10 , G11C16/06
CPC分类号： G06F12/0246 , G06F11/1012 , G06F12/0238 , G06F2212/1032 , G06F2212/1041 , G06F2212/403 , G06F2212/7202 , G06F2212/7207 , G11C16/10 , G11C16/3459 , G11C16/349
摘要： Examples are disclosed for techniques associated with protecting system critical data written to non-volatile memory. In some examples, system critical data may be written to a non-volatile memory using a first data protection scheme. User data that includes non-system critical data may also be written to the non-volatile memory using a second data protection scheme. For these examples, both data protection schemes may have a same given data format size. Various examples are provided for use of the first data protection scheme that may provide enhanced protection for the system critical data compared to protection provided to user data using the second data protection scheme. Other examples are described and claimed.
摘要翻译：公开了与保护写入非易失性存储器的系统关键数据相关的技术的示例。在一些示例中，可以使用第一数据保护方案将系统关键数据写入非易失性存储器。包括非系统关键数据的用户数据也可以使用第二数据保护方案写入非易失性存储器。对于这些示例，两个数据保护方案可以具有相同的给定数据格式大小。为使用第一数据保护方案提供了各种示例，该方案可以与使用第二数据保护方案提供给用户数据的保护相比提供对系统关键数据的增强保护。其他的例子被描述和要求保护。

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