专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

SG11201600809XA DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT 未知
公开(公告)号：SG11201600809XA
公开(公告)日：2016-03-30
申请号：SG11201600809X
申请日：2014-08-06
申请人： RIVERS DOYLE , RUBY PAUL D , ANANDARAJ RAMALINGAM , SUNDARAM RAJESH , WALKER JULIE M
发明人： RIVERS DOYLE , RUBY PAUL D , ANANDARAJ RAMALINGAM , SUNDARAM RAJESH , WALKER JULIE M
IPC分类号： G06F13/14
摘要： Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

2. 发明申请

WO2015047630A1 REFRESH OF DATA STORED IN A CROSS-POINT NON-VOLATILE MEMORY 审中-公开
标题翻译：刷新存储在交叉点非易失性存储器中的数据
公开(公告)号：WO2015047630A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/052746
申请日：2014-08-26
申请人： INTEL CORPORATION , PANGAL, Kiran , RAMANUJAN, Raj K. , FABER, Robert W. , SUNDARAM, Rajesh
发明人： PANGAL, Kiran , RAMANUJAN, Raj K. , FABER, Robert W. , SUNDARAM, Rajesh
IPC分类号： G11C13/00 , G11C11/21
CPC分类号： G11C13/0033 , G11C13/0004 , G11C2013/0076
摘要： Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.
摘要翻译：本文公开了包括与刷新存储器单元相关联的系统，方法和装置的实施例。在实施例中，存储器控制器可以被配置为对诸如相变存储器（PCM）的交叉点非易失性存储器中的一个或多个存储器单元执行读取操作。一个或多个存储单元可以具有分别设置为第一阈值电压或第二阈值电压的电压值。基于读取，存储器控制器可以识别被设置为第二阈值电压的交叉点非易失性存储器中的存储器单元，并且在不改变这些存储器单元的电压值的情况下刷新那些单元的电压值交叉点非易失性存储器被设置为第一阈值电压。可以描述或要求保护其他实施例。

3. 发明申请

WO2012067871A2 PIPELINE ARCHITECTURE FOR SCALABLE PERFORMANCE ON MEMORY 审中-公开
标题翻译：用于存储器可扩展性能的管道结构
公开(公告)号：WO2012067871A2
公开(公告)日：2012-05-24
申请号：PCT/US2011/059529
申请日：2011-11-07
申请人： INTEL CORPORATION , SUNDARAM, Rajesh , KAU, Derchang , ZIMMERMAN, David J.
发明人： SUNDARAM, Rajesh , KAU, Derchang , ZIMMERMAN, David J.
IPC分类号： G11C13/02
CPC分类号： G11C13/0004 , G06F2213/0038 , G11C7/1039 , G11C13/0061 , G11C13/0069
摘要： An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.
摘要翻译：提出了一种用于数据存储的设备。在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。

4. 发明申请

WO2015021171A1 DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT 审中-公开
标题翻译：设备，系统和减少芯片选择的方法
公开(公告)号：WO2015021171A1
公开(公告)日：2015-02-12
申请号：PCT/US2014/049965
申请日：2014-08-06
申请人： RIVERS, Doyle , RUBY, Paul D. , ANANDARAJ, Ramalingam , SUNDARAM, Rajesh , WALKER, Julie M.
发明人： RIVERS, Doyle , RUBY, Paul D. , ANANDARAJ, Ramalingam , SUNDARAM, Rajesh , WALKER, Julie M.
IPC分类号： G06F13/14
CPC分类号： G06F13/4247 , G06F13/14 , G06F13/385
摘要： Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.
摘要翻译：描述了芯片选择的几种系统和方法。在一种这样的方法中，设备维护两个标识符（ID_a和ID_m）。当设备接收到命令时，它检查ID_a和ID_m相对于第三参考标识符（ID_s）的值。如果ID_a或ID_m等于ID_s，则设备执行该命令，否则设备将忽略该命令。通过使用两种不同的识别方法，系统具有选择激活设备的选项，能够以快速方式选择多个设备和单个设备之间进行选择性切换。在另一种这样的方法中，设备可以具有存储诸如ID_a的标识信息的持久区域。因此，系统功能可以独立于与系统中所有设备的初始ID_a分配所需的物理或逻辑组件相关联的任何缺陷/边际。

5. 发明申请

WO2014164099A1 REDUCED UNCORRECTABLE MEMORY ERRORS 审中-公开
标题翻译：减少不可避免的内存错误
公开(公告)号：WO2014164099A1
公开(公告)日：2014-10-09
申请号：PCT/US2014/020549
申请日：2014-03-05
申请人： INTEL CORPORATION , PANGAL, Kiran , DAMLE, Prashant S. , SUNDARAM, Rajesh , QAWAMI, Shekoufeh , WALKER, Julie M. , RIVERS, Doyle
发明人： PANGAL, Kiran , DAMLE, Prashant S. , SUNDARAM, Rajesh , QAWAMI, Shekoufeh , WALKER, Julie M. , RIVERS, Doyle
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1044 , G06F11/1048 , G06F11/1068 , H03M13/05 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27 , H03M13/6508
摘要： Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
摘要翻译：可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误的存储器阵列。然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。

6. 发明申请

WO2013101196A1 PHASE CHANGE MEMORY WITH SWITCH (PCMS) WRITE ERROR DETECTION 审中-公开
标题翻译：相位变化记忆与开关（PCMS）写入错误检测
公开(公告)号：WO2013101196A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068139
申请日：2011-12-30
申请人： INTEL CORPORATION , QAWAMI, Shekoufeh , SUNDARAM, Rajesh
发明人： QAWAMI, Shekoufeh , SUNDARAM, Rajesh
IPC分类号： G11C29/00 , G11C13/02 , G06F11/16
CPC分类号： G06F11/1048 , G06F11/073 , G06F11/0763 , G06F11/1068 , G11C13/0004
摘要： Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。还公开并要求保护其他实施例。

7. 发明申请

WO2013100909A1 ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的自适应配置
公开(公告)号：WO2013100909A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067407
申请日：2011-12-27
申请人： INTEL CORPORATION , QAWAMI, Shekoufeh , SUNDARAM, Rajesh , ZIMMERMAN, David J. , FANNING, Blaise
发明人： QAWAMI, Shekoufeh , SUNDARAM, Rajesh , ZIMMERMAN, David J. , FANNING, Blaise
IPC分类号： G11C16/06 , G11C13/02 , G06F12/00 , G06F9/06
CPC分类号： G11C13/0038 , G06F1/3275 , G06F9/30101 , G06F12/0246 , G11C13/0004 , G11C13/0033 , G11C16/06 , Y02D10/14
摘要： Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
摘要翻译：公开了用于非易失性存储器的自适应配置的示例。示例包括配置为包括默认值和更新值以指示非易失性存储器的一个或多个配置的模式寄存器。这些示例还可以包括可以指示存储器地址长度和/或操作功率状态的配置表中维护的可发现功能。

8. 发明申请

WO2012067871A3 PIPELINE ARCHITECTURE FOR SCALABLE PERFORMANCE ON MEMORY 审中-公开
标题翻译：用于扩展存储器性能的流水线架构
公开(公告)号：WO2012067871A3
公开(公告)日：2012-07-12
申请号：PCT/US2011059529
申请日：2011-11-07
申请人： INTEL CORP , SUNDARAM RAJESH , KAU DERCHANG , ZIMMERMAN DAVID J
发明人： SUNDARAM RAJESH , KAU DERCHANG , ZIMMERMAN DAVID J
IPC分类号： G11C13/02
CPC分类号： G11C13/0004 , G06F2213/0038 , G11C7/1039 , G11C13/0061 , G11C13/0069
摘要： An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.
摘要翻译：提出了一种用于数据存储的装置。在一个实施例中，该装置包括具有相变存储器存储元件的相变存储器装置。该装置还包括控制逻辑，用于控制两个或更多个设置的流水线以交错方式服务于存储器请求，使得存储器请求的设置操作在不同的时间开始。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式