会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Integration of SAC and salicide processes by combining hard mask and
poly definition
    • 通过组合硬掩模和聚合物定义来整合SAC和自杀化合物过程
    • US6015730A
    • 2000-01-18
    • US34926
    • 1998-03-05
    • Chen-Jong WangJenn Ming HuangChue San Yoo
    • Chen-Jong WangJenn Ming HuangChue San Yoo
    • H01L21/02H01L21/336H01L21/60H01L21/768H01L21/8242H01L21/8247H01L21/3205H01L21/4763
    • H01L27/11526H01L21/76897H01L27/10873H01L27/11543H01L29/665H01L21/76895H01L28/60
    • A process and structure are described wherein logic and memory share the same chip. Contacts to the memory circuits are made using the SAC process, thus ensuring maximum density, while contacts to the logic circuits are made using the SALICIDE process, thus ensuring high performance. The two processes have been integrated within a single chip by first depositing the various layers needed by the gate pedestals in both the logic and the memory areas and then forming the two sets of gate pedestals in separate steps. Gates located in the logic area are formed only from polysilicon while those located in the memory areas also have an overlay of tungsten silicide topped by a hard mask of silicon nitride. With the two sets of gates in place, source/drain regions are formed in the usual way. This includes growing of silicon nitride spacers on the vertical sides of the pedestals. The pedestals in the memory area are much longer than those in the logic area since they extend all the way to the top of the hard masks. The pedestals, on the memory side only, are given a protective coating of oxide (RPO). This allows the SALICIDE process to be selectively applied to only the logic side. Then, while the logic side is protected, the SAC process is applied to the memory side. This process is self-aligning. The long spacers define the contact holes and the hard masks allow oversize openings to be etched without the danger of shorting through to the pedestals.
    • 描述了其中逻辑和存储器共享相同芯片的过程和结构。 与存储器电路的接触使用SAC工艺制成,从而确保了最大密度,同时使用SALICIDE工艺进行与逻辑电路的接触,从而确保了高性能。 通过首先将逻辑和存储区域中的栅极基座所需的各种层淀积,然后在分开的步骤中形成两组栅极基座,将这两个工艺集成在单个芯片内。 位于逻辑区域中的栅极仅由多晶硅形成,而位于存储区域中的栅极也具有由氮化硅硬掩模顶上的硅化钨覆盖层。 通过两组门就位,源/漏区以常规方式形成。 这包括在基座的垂直侧上生长氮化硅间隔物。 存储区中的基座比逻辑区域中的基座长得多,因为它们一直延伸到硬掩模的顶部。 仅在记忆方面的基座被赋予氧化物保护层(RPO)。 这允许将SALICIDE过程选择性地仅应用于逻辑侧。 然后,当逻辑侧被保护时,SAC进程被应用于存储器侧。 这个过程是自调整的。 长的间隔件限定接触孔,并且硬掩模允许蚀刻大尺寸的开口,而不会短路到基座的危险。
    • 2. 发明授权
    • Photomask haze reduction via ventilation
    • 通过透光光掩模雾化
    • US07839480B2
    • 2010-11-23
    • US11740166
    • 2007-04-25
    • Chue San Yoo
    • Chue San Yoo
    • G03B27/42
    • G03F1/64
    • Where a framed pellicle is mounted on a photomaps, the framed pellicle comprises a pellicle frame and a pellicle membrane coupled to the pellicle frame, the pellicle frame has first and second apertures each communicating a first space surrounded by the photomask and the framed pellicle with a second space outside of the framed pellicle, exposing a photoresist layer formed on a substrate by flowing gas from within the first space to outside the framed pellicle through the first aperture while simultaneously exposing the photoresist layer to ultraviolet light through the pellicle membrane and the photomask.
    • 在框架防护薄膜组件安装在照片上的情况下,框架防护薄膜组件包括防护薄膜组件框架和联接到防护薄膜框架上的防护薄膜组件,防护薄膜框架具有第一和第二孔,每个孔与光掩模和框架防护薄膜组件包围的第一空间与 在框架防护薄膜外部的第二空间,通过将气体从第一空间内流过框架防护薄膜通过第一孔而暴露出形成在基板上的光致抗蚀剂层,同时将光致抗蚀剂层暴露于通过防护薄膜和光掩模的紫外光。
    • 3. 发明授权
    • Mask and blank storage inner gas
    • 面罩和空白存储内部气体
    • US08268541B2
    • 2012-09-18
    • US11733471
    • 2007-04-10
    • Cheng-Ming LinChue San Yoo
    • Cheng-Ming LinChue San Yoo
    • G03F7/20
    • G03F7/70916G03F7/70866
    • The present disclosure provides a lithography apparatus. The lithography apparatus includes a radiation source providing a radiation energy with a wavelength selected from the group consisting of 193 nm, 248 nm, and 365 nm; a lens system configured approximate to the radiation source; a mask chamber proximate to the lens system, configured to hold a mask and operable to provide a single atom gas to the mask chamber; and a substrate stage configured to hold a substrate and receive the radiation energy through the lens system and the mask during an exposing process.
    • 本公开提供一种光刻设备。 光刻设备包括:辐射源,其提供波长选自193nm,248nm和365nm的波长的辐射能; 配置为近似于辐射源的透镜系统; 靠近透镜系统的掩模室,被配置为保持掩模并可操作以向掩模室提供单个原子气体; 以及衬底台,被配置为在曝光过程期间保持衬底并且通过透镜系统和掩模接收辐射能量。
    • 4. 发明申请
    • PHOTOMASK HAZE REDUCTION VIA VENTILATION
    • 照片通过通风降低烟雾
    • US20080266534A1
    • 2008-10-30
    • US11740166
    • 2007-04-25
    • Chue San Yoo
    • Chue San Yoo
    • G03B27/42
    • G03F1/64
    • Where a framed pellicle is mounted on a photomask, the framed pellicle comprises a pellicle frame and a pellicle membrane coupled to the pellicle frame, the pellicle frame has first and second apertures each communicating a first space surrounded by the photomask and the framed pellicle with a second space outside of the framed pellicle, exposing a photoresist layer formed on a substrate by flowing gas from within the first space to outside the framed pellicle through the first aperture while simultaneously exposing the photoresist layer to ultraviolet light through the pellicle membrane and the photomask.
    • 在框架防护薄膜组件安装在光掩模上的情况下,框架防护薄膜组件包括防护薄膜组件框架和联接到防护薄膜框架上的防护薄膜组件,防护薄膜框架具有第一和第二孔,每个孔与光掩模和框架防护薄膜组件包围的第一空间与 在框架防护薄膜外部的第二空间,通过将气体从第一空间内流过框架防护薄膜通过第一孔而暴露出形成在基板上的光致抗蚀剂层,同时将光致抗蚀剂层暴露于通过防护薄膜和光掩模的紫外光。