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1. 发明授权

US09379057B2 Method and structure to reduce the electric field in semiconductor wiring interconnects 有权
标题翻译：降低半导体布线互连电场的方法和结构
公开(公告)号：US09379057B2
公开(公告)日：2016-06-28
申请号：US14474935
申请日：2014-09-02
申请人： Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
发明人： Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L23/528 , H01L21/76804 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76883 , H01L23/5226 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.
摘要翻译：本发明的实施例提供了在后端（BEOL）结构中的通孔和相邻金属线之间的距离增加。铜合金种子层沉积在形成在电介质层中的沟槽中。然后用铜填充沟槽。然后，在退火期间，当锰在介电层中被拉出时，进行退火以形成使用诸如锰的种子层成分的自形成势垒。自形成障碍物设置在电介质层的肩部区域上，增加了通孔及其相邻金属线之间的有效距离。

2. 发明申请

US20160064321A1 METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS 有权
公开(公告)号：US20160064321A1
公开(公告)日：2016-03-03
申请号：US14474935
申请日：2014-09-02
申请人： Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
发明人： Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
IPC分类号： H01L23/528 , H01L23/522 , H01L23/532 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76804 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76883 , H01L23/5226 , H01L23/53228 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.

3. 发明授权

US08835305B2 Method of fabricating a profile control in interconnect structures 有权
标题翻译：在互连结构中制作轮廓控制的方法
公开(公告)号：US08835305B2
公开(公告)日：2014-09-16
申请号：US13562953
申请日：2012-07-31
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
IPC分类号： H01L21/4763 , H01L23/12 , H01L21/768 , H01L23/522
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76813 , H01L21/76831 , H01L21/76844 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.
摘要翻译：可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

4. 发明授权

US07544609B2 Method for integrating liner formation in back end of line processing 有权
标题翻译：在线处理后端整合衬垫形成的方法
公开(公告)号：US07544609B2
公开(公告)日：2009-06-09
申请号：US11673276
申请日：2007-02-09
申请人： Matthew S. Angyal , Habib Hichri , Christopher J. Penny , David K. Watts
发明人： Matthew S. Angyal , Habib Hichri , Christopher J. Penny , David K. Watts
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76877
摘要： A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.
摘要翻译：一种用于在半导体器件的后端行（BEOL）处理中集成帽衬层形成的方法包括在半导体器件的绝缘层内形成沟槽结构，在绝缘层的顶表面上沉积第一衬里材料，包括沟槽的侧壁和底表面，并且用布线金属材料将沟槽部分地填充到与最终预定的线高度相对应的高度。第二衬里材料在布线金属材料上方，并且在第二衬里材料上形成牺牲填充材料。将牺牲填充物平坦化到部分填充沟槽的布线金属材料上的第二衬垫材料的水平面上，其中第二衬垫材料的剩余部分限定了布线金属的盖衬垫。

5. 发明申请

US20080194099A1 Method for Integrating Liner Formation in Back End of Line Processing 有权
标题翻译：在线处理后端集成衬垫形成的方法
公开(公告)号：US20080194099A1
公开(公告)日：2008-08-14
申请号：US11673276
申请日：2007-02-09
申请人： Matthew S. Angyal , Habib Hichri , Christopher J. Penny , David K. Watts
发明人： Matthew S. Angyal , Habib Hichri , Christopher J. Penny , David K. Watts
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/7684 , H01L21/76877
摘要： A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.
摘要翻译：一种用于在半导体器件的后端行（BEOL）处理中集成帽衬层形成的方法包括在半导体器件的绝缘层内形成沟槽结构，在绝缘层的顶表面上沉积第一衬里材料，包括沟槽的侧壁和底表面，并且用布线金属材料将沟槽部分地填充到与最终预定的线高度相对应的高度。第二衬里材料在布线金属材料上方，并且在第二衬里材料上形成牺牲填充材料。将牺牲填充物平坦化到部分填充沟槽的布线金属材料上的第二衬垫材料的水平面上，其中第二衬垫材料的剩余部分限定了布线金属的盖衬垫。

6. 发明申请

US20140035142A1 PROFILE CONTROL IN INTERCONNECT STRUCTURES 有权
标题翻译：互连结构中的配置控制
公开(公告)号：US20140035142A1
公开(公告)日：2014-02-06
申请号：US13562953
申请日：2012-07-31
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76813 , H01L21/76831 , H01L21/76844 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.
摘要翻译：可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。

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