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1. 发明申请

US20090051339A1 DC-DC CONVERTER AND CONTROL CIRCUIT FOR DC-DC CONVERTER 有权
标题翻译： DC-DC转换器的DC-DC转换器和控制电路
公开(公告)号：US20090051339A1
公开(公告)日：2009-02-26
申请号：US12257222
申请日：2008-10-23
申请人： Morihito Hasegawa , Chikara Tsuchiya , Hidenobu Ito
发明人： Morihito Hasegawa , Chikara Tsuchiya , Hidenobu Ito
IPC分类号： G05F1/618
CPC分类号： H02M1/38 , H03K2017/307
摘要： A DC-DC converter prevents through current from flowing in an output transistor. A first transistor receives an input voltage. A second transistor is connected to the first transistor. A comparator is connected to the second transistor. The comparator detects current flowing through a choke coil based on the potential difference between two terminals of the second transistor to generate a switching control signal for turning the second transistor on and off. The second transistor and the comparator form an ideal diode. A control circuit of the DC-DC converter generates an activation signal for turning the first transistor on and off based on a pulse signal to keep an output voltage constant. A through current prevention pulse generation circuit generates a pulse signal for turning off the second transistor from before the first transistor is turned on to after the first transistor is turned on.
摘要翻译： DC-DC转换器防止直流电流流入输出晶体管。第一晶体管接收输入电压。第二晶体管连接到第一晶体管。比较器连接到第二晶体管。比较器基于第二晶体管的两个端子之间的电位差来检测流过扼流线圈的电流，以产生用于使第二晶体管接通和关断的开关控制信号。第二个晶体管和比较器构成一个理想的二极管。 DC-DC转换器的控制电路基于脉冲信号产生用于使第一晶体管导通和截止的激活信号，以保持输出电压恒定。通过电流防止脉冲产生电路在第一晶体管导通之后到第一晶体管导通之后产生用于使第二晶体管截止的脉冲信号。

2. 发明授权

US07358946B2 Offset cancel circuit of voltage follower equipped with operational amplifier 失效
标题翻译：具有运算放大器的电压跟随器的偏移消除电路
公开(公告)号：US07358946B2
公开(公告)日：2008-04-15
申请号：US11181774
申请日：2005-07-15
申请人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
发明人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , H03F3/45753
摘要： A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
摘要翻译：差分放大电路11包括具有分别连接MOS晶体管M 8和M 9的漏极的第一和第二电流端的电流镜电路，以及具有栅极的一对差分MOS晶体管M 1和M 2，开关SW 1连接。参考电位Vref被施加到MOS晶体管M 9的栅极。开关SW 2连接在输出缓冲器电路12的输出VO和MOS晶体管M 1的栅极之间，开关SW 3连接在输出VO和MOS晶体管M8的栅极之间。在偏移取消准备期间，开关SW 1和SW 3接通，开关SW 2断开。接下来，开关SW 1至SW 3翻转，从而输出偏移抵消电位VO。

3. 发明授权

US07242427B2 X-Y address type solid-state image pickup device with an image averaging circuit disposed in the noise cancel circuit 有权
标题翻译：具有设置在噪声消除电路中的图像平均电路的X-Y地址型固态图像拾取装置
公开(公告)号：US07242427B2
公开(公告)日：2007-07-10
申请号：US10055901
申请日：2002-01-28
申请人： Masatoshi Kokubun , Katsuyosi Yamamoto , Shinya Udo , Jun Funakoshi , Chikara Tsuchiya
发明人： Masatoshi Kokubun , Katsuyosi Yamamoto , Shinya Udo , Jun Funakoshi , Chikara Tsuchiya
IPC分类号： H04N5/217
CPC分类号： H04N5/378 , H04N5/343 , H04N5/347
摘要： The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiode 10, a source follower amplifier 14 for converting an electric charge of the photodiode 10 into a voltage and amplifying it to output image data, and a horizontal selection transistor 16 for outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuit 6 has a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.
摘要翻译：本发明涉及一种通过CMOS工艺制造的XY地址型固态摄像装置，其目的是提供一种XY地址型固态摄像装置，其中芯片面积不增加，制造成本被抑制，并且可以执行图像平均处理。像素区域Pmn以由水平选择线RWm和垂直选择线CLn限定的区域中的矩阵形式排列。每个像素区Pmn包括光电二极管10，用于将光电二极管10的电荷转换成电压并放大以输出图像数据的源极跟随器放大器14以及用于将图像数据输出到预定的水平选择晶体管16 垂直选择线CLn之一。放大器/噪声消除电路6具有内置图像平均电路，用于对从多个像素区域Pmn中的至少两个输出的图像数据进行平均处理。

4. 发明授权

US06946905B2 Offset cancel circuit of voltage follower equipped with operational amplifier 有权
标题翻译：具有运算放大器的电压跟随器的偏移消除电路
公开(公告)号：US06946905B2
公开(公告)日：2005-09-20
申请号：US10301649
申请日：2002-11-22
申请人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
发明人： Masatoshi Kokubun , Shinya Udo , Chikara Tsuchiya
IPC分类号： G09G3/20 , G09G3/36 , H03F1/02 , H03F1/34 , H03F3/34 , H03F3/345 , H03F3/45 , H03F3/50 , H03L5/00
CPC分类号： G09G3/3685 , H03F3/45753
摘要： A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.
摘要翻译：差分放大电路11包括具有分别连接MOS晶体管M 8和M 9的漏极的第一和第二电流端的电流镜电路，以及具有栅极的一对差分MOS晶体管M 1和M 2，开关SW 1连接。参考电位Vref被施加到MOS晶体管M 9的栅极。开关SW 2连接在输出缓冲器电路12的输出VO和MOS晶体管M 1的栅极之间，开关SW 3连接在输出VO和MOS晶体管M8的栅极之间。在偏移取消准备期间，开关SW 1和SW 3接通，开关SW 2断开。接下来，开关SW 1至SW 3翻转，从而输出偏移抵消电位VO。

5. 发明授权

US06747700B1 Solid state image pickup apparatus having a plurality of split buses 有权
标题翻译：具有多个分裂总线的固态摄像装置
公开(公告)号：US06747700B1
公开(公告)日：2004-06-08
申请号：US09534231
申请日：2000-03-24
申请人： Jun Funakoshi , Chikara Tsuchiya
发明人： Jun Funakoshi , Chikara Tsuchiya
IPC分类号： H04N5335
CPC分类号： H04N5/335 , H04N5/374 , H04N5/3742
摘要： In a solid state image pickup apparatus, a read bus consists of, for instance, four lines of split buses and one line of integrated bus. This integrated bus can be connected to the four lines of split buses. Electrical connection between the integrated bus and each of the split buses is selected by a corresponding switching element. Thus, the number of switching elements connected to one split bus can be reduced and hence the capacitance of the split bus can be reduced. This allows pixel signals to be read out at a higher speed.
摘要翻译：在固态图像拾取装置中，读取总线由例如四条分裂总线和一条集成总线组成。该集成总线可以连接到四条分路总线。通过相应的开关元件选择集成总线与每个分接总线之间的电连接。因此，可以减少连接到一个分离总线的开关元件的数量，因此可以减小分流总线的电容。这允许以更高的速度读出像素信号。

6. 发明授权

US5220559A Neuron architecture 失效
标题翻译： NEURON建筑
公开(公告)号：US5220559A
公开(公告)日：1993-06-15
申请号：US400826
申请日：1989-08-30
申请人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
发明人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.

7. 发明授权

US5142666A Learning system in a neuron computer 失效
标题翻译：神经电脑学习系统
公开(公告)号：US5142666A
公开(公告)日：1992-08-25
申请号：US486644
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号： G06G7/60 , G06F15/18 , G06N3/02 , G06N3/04 , G06N3/08 , G06N99/00
CPC分类号： G06N3/04
摘要： A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.

8. 发明授权

US4551644A Field effect transistor gate circuit for analog signals 失效
标题翻译：场效应晶体管门电路用于模拟信号
公开(公告)号：US4551644A
公开(公告)日：1985-11-05
申请号：US547236
申请日：1983-10-31
申请人： Eiji Nishimori , Chikara Tsuchiya , Yoshiaki Sano
发明人： Eiji Nishimori , Chikara Tsuchiya , Yoshiaki Sano
IPC分类号： H03K17/14 , H03K17/687 , H03K17/16 , H03K17/693
CPC分类号： H03K17/687 , H03K17/145
摘要： A gate circuit for analog signals composed of field effect transistors is provided. The analog signal is switched on and off by variation of the conductance of the FETs. Distortion of the signal is a crucial problem for such circuits, which is overcome by detecting the voltages at both the source and drain sides of the switching transistor which controls the signals to be on and off, and by feeding the voltages back to the gate of the switching transistor. The inner resistance of the switching transistor when it is in the on state is reduced, and becomes symmetric at both sides of V.sub.DS0. As a result the second order distortion is greatly reduced.
摘要翻译：提供由场效应晶体管组成的模拟信号的门电路。模拟信号通过FET的电导的变化而导通和截止。信号的失真是这种电路的关键问题，通过检测开关晶体管的源极和漏极两端的电压来控制信号的导通和断开，并通过将电压馈送回到开关晶体管。开关晶体管处于导通状态时的内阻减小，并在VDS0的两侧变为对称。结果，二阶失真大大降低。

9. 发明授权

US4525637A Integrated circuit having an input voltage-clamping function and an input current-detecting function 失效
标题翻译：具有输入电压钳位功能和输入电流检测功能的集成电路
公开(公告)号：US4525637A
公开(公告)日：1985-06-25
申请号：US425654
申请日：1982-09-28
申请人： Yoshiaki Sano , Chikara Tsuchiya , Osamu Maida
发明人： Yoshiaki Sano , Chikara Tsuchiya , Osamu Maida
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L29/73 , H01L29/861 , H03K5/08 , H03K17/30 , H03K5/153
CPC分类号： H03K5/08 , H03K17/30
摘要： An integrated circuit has an input voltage-clamping function and an input current-detecting function. A voltage-clamping circuit is provided for clamping a voltage at the input signal terminal, the voltage being clamped in response to an input current greater than a first predetermined value supplied to the input terminal. A current detecting circuit is also provided for detecting whether the input current supplied to the input terminal is greater than a second predetermined value, whereby the single input terminal for signals is used for both functions, i.e., the input voltage-clamping function and the input current-detecting function.
摘要翻译：集成电路具有输入电压钳位功能和输入电流检测功能。提供钳位电路用于钳位输入信号端子处的电压，该电压响应于大于提供给输入端子的第一预定值的输入电流被钳位。还提供电流检测电路，用于检测提供给输入端的输入电流是否大于第二预定值，由此用于信号的单个输入端用于两个功能，即输入电压钳位功能和输入电流检测功能。

10. 发明申请

US20070216381A1 Linear regulator circuit 审中-公开
标题翻译：线性稳压电路
公开(公告)号：US20070216381A1
公开(公告)日：2007-09-20
申请号：US11499718
申请日：2006-08-07
申请人： Chikara Tsuchiya , Eiji Nishimori
发明人： Chikara Tsuchiya , Eiji Nishimori
IPC分类号： G05F1/00
CPC分类号： G05F1/575
摘要： A linear regulator circuit for suppressing power supply noise that propagates to an output voltage. An LDO circuit functioning as the linear regulator circuit is provided with an output transistor including a source for receiving input voltage, a drain for outputting the output voltage, and a control terminal. An error amplifier powered by the input voltage generates a control voltage for controlling the output transistor based on a potential difference between a feedback voltage, which corresponds to the output voltage, and a reference voltage. A first capacitor and a resistor are connected in series between the source of the output transistor and an output terminal of the error amplifier.
摘要翻译：一种用于抑制传播到输出电压的电源噪声的线性调节器电路。用作线性调节器电路的LDO电路设置有包括用于接收输入电压的源极，用于输出输出电压的漏极和控制端子的输出晶体管。由输入电压供电的误差放大器基于对应于输出电压的反馈电压与参考电压之间的电位差产生用于控制输出晶体管的控制电压。第一电容器和电阻器串联连接在输出晶体管的源极和误差放大器的输出端子之间。

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