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1. 发明授权

US5131072A Neurocomputer with analog signal bus 失效
标题翻译：具有模拟信号总线的神经元
公开(公告)号：US5131072A
公开(公告)日：1992-07-14
申请号：US474055
申请日：1990-04-30
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Yoshihide Sugiura , Kazuo Asakawa , Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Chikara Tsuchiya , Katsuya Ishikawa , Hiromu Iwamoto
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/063 , G06N3/04 , G06N3/0635
摘要： An analogue neuron processor (ANP) performs an operation of sum-of-products of a time divisional analog input signal sequentially input from an analog signal bus and weight data and output an analog signal to an analog signal bus through a nonlinear circuit. A layered type or a feedback type neural network is formed of ANPs. The neural network reads necessary control data from a control pattern memory under the control of micro sequencer and reads the necessary weight data from the weight memory thereby realizing a neuron computer. The neuron computer connects a plurality of ANPs by using a single analog bus, thereby greatly decreasing the number of the wires used for the neural network and also decreasing the size of the circuit. A plurality of ANPs in a single layer simultaneously receives analog signal from an analog bus and carries out a parallel operation in the same time period and ANPs in different layers perform a parallel operation in a pipeline manner, thereby increasing a speed of an operation. Accordingly, the prsent invention can provide a neuron computer with a high practicality.

2. 发明授权

US5220559A Neuron architecture 失效
标题翻译： NEURON建筑
公开(公告)号：US5220559A
公开(公告)日：1993-06-15
申请号：US400826
申请日：1989-08-30
申请人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
发明人： Hiroyuki Tsuzuki , Hideichi Endo , Takashi Kawasaki , Toshiharu Matsuda , Kazuo Asakawa , Hideki Kato , Hideki Yoshizawa , Hiroki Iciki , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa , Yoshihide Sugiura
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.

3. 发明授权

US5142666A Learning system in a neuron computer 失效
标题翻译：神经电脑学习系统
公开(公告)号：US5142666A
公开(公告)日：1992-08-25
申请号：US486644
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号： G06G7/60 , G06F15/18 , G06N3/02 , G06N3/04 , G06N3/08 , G06N99/00
CPC分类号： G06N3/04
摘要： A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.

4. 发明授权

US5216746A Error absorbing system in a neuron computer 失效
标题翻译：神经电脑中的错误吸收系统
公开(公告)号：US5216746A
公开(公告)日：1993-06-01
申请号：US486647
申请日：1990-02-28
申请人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人： Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号： G06N3/04
CPC分类号： G06N3/04
摘要： An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.

5. 发明授权

US4412237A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4412237A
公开(公告)日：1983-10-25
申请号：US143472
申请日：1980-08-29
申请人： Nobutake Matsumura , Ryusuke Hoshikawa , Yoshihide Sugiura , Hiroaki Ichikawa , Syoji Sato
发明人： Nobutake Matsumura , Ryusuke Hoshikawa , Yoshihide Sugiura , Hiroaki Ichikawa , Syoji Sato
IPC分类号： H01L21/822 , G11C5/06 , G11C11/412 , G11C11/417 , G11C11/418 , H01L21/82 , H01L27/04 , H01L27/118 , H01L29/78 , H03K3/356 , H01L27/02
CPC分类号： H01L27/11807 , G11C11/412 , G11C11/417 , G11C11/418 , G11C5/063 , H03K3/356104 , Y10S257/923
摘要： Disclosed is a semiconductor device having a large number of basic cells, wherein a plurality of basic cells arranged along rows of a semiconductor substrate form a basic cell array and a plurality of the basic cell arrays are arranged along columns of the substrate, and further including spaces formed between each adjoining column. Each basic cell is comprised of first and second P-channel MIS transistors and first and second N-channel MIS transistors. The gates of both the first P-channel and the first N-channel MIS transistors form a first single common gate, and the gates of both the second P-channel and the second N-channel MIS transistors form a second single common gate. The sources or the drains of both the first P-channel and the second P-channel MIS transistors form a first single common source or drain, and the sources or the drains of both the first N-channel and the second N-channel MIS transistors form a second single common source or drain. Each of the first and second single common gates has two terminal electrodes at both sides of respective basic cell array and a central terminal electrode at the center of the respective basic cell array. Further, each of the basic cells includes a small space extending between both sides of the basic cell array, which space can be utilized as a field for distributing, along a row, interconnecting lines.
摘要翻译： PCT No.PCT / JP78 / 00048 Sec。 371日期1979年8月29日第 102（e）日期1979年8月29日PCT提交1978年12月11日PCT公布。出版物WO79 / 00461 日期：1979年7月26日。公开是具有大量基本单元的半导体器件，其中沿着半导体衬底的行排列的多个基本单元形成基本单元阵列，并且多个基本单元阵列沿着列并且还包括在每个相邻的柱之间形成的空间。每个基本单元包括第一和第二P沟道MIS晶体管以及第一和第二N沟道MIS晶体管。第一P沟道和第一N沟道MIS晶体管的栅极形成第一单个公共栅极，并且第二P沟道和第二N沟道MIS晶体管的栅极形成第二单个公共栅极。第一P沟道和第二P沟道MIS晶体管的源极或漏极形成第一单个公共源极或漏极，并且第一N沟道和第二N沟道MIS晶体管的源极或漏极形成第二个单一的共同来源或渠道。第一和第二单个公共门中的每一个在各个基本单元阵列的两侧具有两个端子电极和位于各个基本单元阵列的中心的中心端子电极。此外，每个基本单元包括在基本单元阵列的两侧之间延伸的小空间，该空间可以用作沿着一行互连线分布的场。

6. 发明授权

US4791474A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4791474A
公开(公告)日：1988-12-13
申请号：US131323
申请日：1987-12-08
申请人： Yoshihide Sugiura , Hiroaki Ichikawa , Nobutake Matsumura , Nobuo Sasaki
发明人： Yoshihide Sugiura , Hiroaki Ichikawa , Nobutake Matsumura , Nobuo Sasaki
IPC分类号： H01L27/092 , H01L21/82 , H01L21/8238 , H01L23/525 , H01L23/535 , H01L27/118 , H01L27/12 , H01L29/78 , H01L29/786 , H01L27/04
CPC分类号： H01L27/11807 , H01L23/525 , H01L23/535 , H01L2924/0002
摘要： A semiconductor integrated circuit device includes basic semiconductor elements arranged regularly in lines and rows and located at intersecting points of the lines and rows and wiring conductor layers arranged among the basic semiconductor elements regularly in lines and rows. In this semiconductor integrated circuit device, according to a desired logic operation, wiring conductor layers are cut or contact holes are formed on the wiring conductor layers to form wiring metal layers and connect the basic semiconductor elements to one another, so that an integrated circuit chip capable of performing the desired logic operation is obtained.
摘要翻译：半导体集成电路器件包括以行和行规则排列并且以行和行规则地布置在基本半导体元件中的线和行的交叉点和布线导体层之间的基本半导体元件。在该半导体集成电路器件中，根据期望的逻辑运算，切断布线导体层，或者在布线导体层上形成接触孔，形成配线用金属层，并将基底半导体元件彼此连接，使集成电路芯片能够实现所需的逻辑运算。

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