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1. 发明申请

US20080303102A1 Strained Isolation Regions 有权
标题翻译：应变隔离区域
公开(公告)号：US20080303102A1
公开(公告)日：2008-12-11
申请号：US11759791
申请日：2007-06-07
申请人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
发明人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
摘要翻译：提供了具有局部应力源的隔离沟槽。根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。然后将电介质材料凹入到衬底的表面下方。在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。应力膜也可以在晶体管或其它半导体结构上延伸。

2. 发明授权

US08736016B2 Strained isolation regions 有权
标题翻译：应变隔离区
公开(公告)号：US08736016B2
公开(公告)日：2014-05-27
申请号：US11759791
申请日：2007-06-07
申请人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
发明人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
摘要翻译：提供了具有局部应力源的隔离沟槽。根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。然后将电介质材料凹入到衬底的表面下方。在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。应力膜也可以在晶体管或其它半导体结构上延伸。

3. 发明申请

US20130330906A1 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION 有权
标题翻译：半导体集成电路制造方法
公开(公告)号：US20130330906A1
公开(公告)日：2013-12-12
申请号：US13490635
申请日：2012-06-07
申请人： Weibo Yu , Ming-His Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Ming-His Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L29/66795
摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.
摘要翻译：公开了制造半导体IC的方法。该方法包括接收设备。该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

4. 发明授权

US08735252B2 Method of semiconductor integrated circuit fabrication 有权
标题翻译：半导体集成电路制造方法
公开(公告)号：US08735252B2
公开(公告)日：2014-05-27
申请号：US13490635
申请日：2012-06-07
申请人： Weibo Yu , Ming-Hsi Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Ming-Hsi Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , H01L29/66795
摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.
摘要翻译：公开了制造半导体IC的方法。该方法包括接收设备。该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

5. 发明授权

US09054130B2 Bottle-neck recess in a semiconductor device 有权
标题翻译：半导体器件中的瓶颈凹槽
公开(公告)号：US09054130B2
公开(公告)日：2015-06-09
申请号：US12841763
申请日：2010-07-22
申请人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
发明人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
IPC分类号： H01L21/302 , H01L29/66 , H01L21/306 , H01L21/3065 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66636
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.
摘要翻译：本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域在硅衬底中，对硅衬底中的凹陷区域进行非偏置蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中生长半导体材料在硅衬底中。一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

6. 发明授权

US07186662B2 Method for forming a hard mask for gate electrode patterning and corresponding device 有权
标题翻译：用于形成用于栅极电极图案化的硬掩模和相应装置的方法
公开(公告)号：US07186662B2
公开(公告)日：2007-03-06
申请号：US10964841
申请日：2004-10-13
申请人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
IPC分类号： H01L21/461
CPC分类号： H01L21/28123 , H01L21/0217 , H01L21/28035 , H01L21/31608 , H01L21/3185
摘要： A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.
摘要翻译：公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

7. 发明申请

US20110049567A1 BOTTLE-NECK RECESS IN A SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件中的瓶颈记录
公开(公告)号：US20110049567A1
公开(公告)日：2011-03-03
申请号：US12841763
申请日：2010-07-22
申请人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
发明人： Eric Peng , Chao-Cheng Chen , Ming-Hua Yu , Ying Hao Hsieh , Tze-Liang Lee , Chii-Horng Li , Syun-Ming Jang , Shih-Hao Lo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/66636
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.
摘要翻译：本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域在硅衬底中，对硅衬底中的凹部进行无偏压蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中形成半导体材料在硅衬底中。一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

8. 发明申请

US20060081917A1 Method for forming a hard mask for gate electrode patterning and corresponding device 有权
标题翻译：用于形成用于栅极电极图案化的硬掩模和相应装置的方法
公开(公告)号：US20060081917A1
公开(公告)日：2006-04-20
申请号：US10964841
申请日：2004-10-13
申请人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Jen Chen , Tze-Liang Lee , Chao-Cheng Chen , Shih-Chang Chen
IPC分类号： H01L29/76
CPC分类号： H01L21/28123 , H01L21/0217 , H01L21/28035 , H01L21/31608 , H01L21/3185
摘要： A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.
摘要翻译：公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

9. 发明授权

US08748989B2 Fin field effect transistors 有权
标题翻译： Fin场效应晶体管
公开(公告)号：US08748989B2
公开(公告)日：2014-06-10
申请号：US13407507
申请日：2012-02-28
申请人： Yu Chao Lin , Chih-Tang Peng , Shun-Hui Yang , Ryan Chia-Jen Chen , Chao-Cheng Chen
发明人： Yu Chao Lin , Chih-Tang Peng , Shun-Hui Yang , Ryan Chia-Jen Chen , Chao-Cheng Chen
IPC分类号： H01L21/70
CPC分类号： H01L21/3065 , H01L21/76224 , H01L21/823431 , H01L21/823821 , H01L27/0886 , H01L27/0924
摘要： The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin.
摘要翻译：本发明涉及鳍状场效应晶体管（FinFET）。 FinFET的示例性结构包括：包括主表面的衬底; 多个第一沟槽，具有第一宽度并从所述衬底主表面向下延伸到第一高度，其中相邻第一沟槽之间的第一空间限定第一鳍片; 以及多个第二沟槽，其具有小于第一宽度的第二宽度并且从所述衬底主表面向下延伸到大于所述第一高度的第二高度，其中相邻第二沟槽之间的第二空间限定第二鳍片。

10. 发明授权

US07833853B2 Method of defining gate structure height for semiconductor devices 有权
标题翻译：定义半导体器件栅极结构高度的方法
公开(公告)号：US07833853B2
公开(公告)日：2010-11-16
申请号：US12339483
申请日：2008-12-19
申请人： Ryan Chia-Jen Chen , Yih-Ann Lin , Joseph Lin , Jr Jung Lin , Yu Chao Lin , Chao-Cheng Chen , Kuo-Tai Huang
发明人： Ryan Chia-Jen Chen , Yih-Ann Lin , Joseph Lin , Jr Jung Lin , Yu Chao Lin , Chao-Cheng Chen , Kuo-Tai Huang
IPC分类号： H01L21/28
CPC分类号： H01L29/7848 , H01L21/28079 , H01L21/28088 , H01L21/28123 , H01L29/165 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/66636
摘要： Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.
摘要翻译：提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。该方法包括在衬底上形成覆盖层并覆盖栅极结构。将涂层回蚀刻以露出栅极结构的一部分。蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。

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